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| author | H.J. Lu <hjl.tools@gmail.com> | 2018-11-05 09:01:26 -0800 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2018-11-05 09:01:43 -0800 |
| commit | e60f4d3bdac25f02875afe36b7436bc2dfbbb978 (patch) | |
| tree | f657bb8dd416d712ec6ad3c6506348b85bd4db1c /gas/config | |
| parent | 713f1b445a18af04eafbf8df6f844bed8243963f (diff) | |
| download | gdb-e60f4d3bdac25f02875afe36b7436bc2dfbbb978.zip gdb-e60f4d3bdac25f02875afe36b7436bc2dfbbb978.tar.gz gdb-e60f4d3bdac25f02875afe36b7436bc2dfbbb978.tar.bz2 | |
x86: Disable GOT relaxation with data prefix
Since linker GOT relaxation isn't valid for 16-bit GOT access, we should
disable GOT relaxation with data prefix.
gas/
PR gas/r23854
* config/tc-i386.c (output_disp): Disable GOT relaxation with
data prefix.
* testsuite/gas/i386/mixed-mode-reloc32.d: Updated.
ld/
PR gas/r23854
* testsuite/ld-i386/i386.exp: Run pr23854.
* testsuite/ld-x86-64/x86-64.exp: Likewwise.
* testsuite/ld-i386/pr23854.d: New file.
* testsuite/ld-i386/pr23854.s: Likewwise.
* testsuite/ld-i386/pr23854.d: Likewwise.
* testsuite/ld-x86-64/pr23854.d: Likewwise.
* testsuite/ld-x86-64/pr23854.s: Likewwise.
Diffstat (limited to 'gas/config')
| -rw-r--r-- | gas/config/tc-i386.c | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index e808d20..7d4ffc8 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -8419,12 +8419,13 @@ output_disp (fragS *insn_start_frag, offsetT insn_start_off) /* Check for "call/jmp *mem", "mov mem, %reg", "test %reg, mem" and "binop mem, %reg" where binop is one of adc, add, and, cmp, or, sbb, sub, xor - instructions. Always generate R_386_GOT32X for - "sym*GOT" operand in 32-bit mode. */ - if ((generate_relax_relocations - || (!object_64bit - && i.rm.mode == 0 - && i.rm.regmem == 5)) + instructions without data prefix. Always generate + R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */ + if (i.prefix[DATA_PREFIX] == 0 + && (generate_relax_relocations + || (!object_64bit + && i.rm.mode == 0 + && i.rm.regmem == 5)) && (i.rm.mode == 2 || (i.rm.mode == 0 && i.rm.regmem == 5)) && ((i.operands == 1 |