diff options
| author | David Guillen Fandos <david@davidgf.net> | 2023-06-15 04:45:03 +0100 |
|---|---|---|
| committer | Maciej W. Rozycki <macro@orcam.me.uk> | 2023-06-15 04:45:03 +0100 |
| commit | df18f71b565c29f6f1ebd385cb1aed97d00e9660 (patch) | |
| tree | 9bf1c937007fab248a8c3cbee838326bac497104 /gas/config | |
| parent | 011365bacac6a95dab2a6a96e96503983682be50 (diff) | |
| download | gdb-df18f71b565c29f6f1ebd385cb1aed97d00e9660.zip gdb-df18f71b565c29f6f1ebd385cb1aed97d00e9660.tar.gz gdb-df18f71b565c29f6f1ebd385cb1aed97d00e9660.tar.bz2 | |
Add MIPS Allegrex CPU as a MIPS2-based CPU
The Allegrex CPU was created by Sony Interactive Entertainment to power
their portable console, the PlayStation Portable.
The pspdev organization maintains all sorts of tools to create software
for said device including documentation.
Signed-off-by: David Guillen Fandos <david@davidgf.net>
Diffstat (limited to 'gas/config')
| -rw-r--r-- | gas/config/tc-mips.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c index 55a116f..0439a3e 100644 --- a/gas/config/tc-mips.c +++ b/gas/config/tc-mips.c @@ -437,6 +437,7 @@ static int mips_32bitmode = 0; || (ISA) == ISA_MIPS64R3 \ || (ISA) == ISA_MIPS64R5 \ || (ISA) == ISA_MIPS64R6 \ + || (CPU) == CPU_ALLEGREX \ || (CPU) == CPU_R5900) \ && ((CPU) != CPU_GS464 \ || (CPU) != CPU_GS464E \ @@ -535,8 +536,9 @@ static int mips_32bitmode = 0; #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU)) /* True, if CPU has support for ldc1 and sdc1. */ -#define CPU_HAS_LDC1_SDC1(CPU) \ - ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900)) +#define CPU_HAS_LDC1_SDC1(CPU) (mips_opts.isa != ISA_MIPS1 \ + && (CPU) != CPU_ALLEGREX \ + && (CPU) != CPU_R5900) /* True if mflo and mfhi can be immediately followed by instructions which write to the HI and LO registers. @@ -561,6 +563,7 @@ static int mips_32bitmode = 0; || mips_opts.isa == ISA_MIPS64R3 \ || mips_opts.isa == ISA_MIPS64R5 \ || mips_opts.isa == ISA_MIPS64R6 \ + || mips_opts.arch == CPU_ALLEGREX \ || mips_opts.arch == CPU_R4010 \ || mips_opts.arch == CPU_R5900 \ || mips_opts.arch == CPU_R10000 \ @@ -20008,6 +20011,7 @@ static const struct mips_cpu_info mips_cpu_info_table[] = /* MIPS II */ { "r6000", 0, 0, ISA_MIPS2, CPU_R6000 }, + { "allegrex", 0, 0, ISA_MIPS2, CPU_ALLEGREX }, /* MIPS III */ { "r4000", 0, 0, ISA_MIPS3, CPU_R4000 }, |