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| author | Andrew Bennett <andrew.bennett@imgtec.com> | 2014-04-23 11:24:30 +0100 |
|---|---|---|
| committer | Andrew Bennett <andrew.bennett@imgtec.com> | 2014-04-23 13:01:18 +0100 |
| commit | 7d64c587c15f290d228ca550bb288d53f0eb2ac4 (patch) | |
| tree | 72600357f6d2371bd27de80b4e69a4216855293a /gas/config | |
| parent | cd0449ab05e9045682a81bf521bd0c8732c98feb (diff) | |
| download | gdb-7d64c587c15f290d228ca550bb288d53f0eb2ac4.zip gdb-7d64c587c15f290d228ca550bb288d53f0eb2ac4.tar.gz gdb-7d64c587c15f290d228ca550bb288d53f0eb2ac4.tar.bz2 | |
Add support for the MIPS eXtended Physical Address (XPA) ASE.
ChangeLog:
binutils/
* doc/binutils.texi: Document the disassemble MIPS XPA instructions
command line option.
gas/
* config/tc-mips.c (options): Add OPTION_XPA and OPTION_NO_XPA.
(md_longopts): Add xpa and no-xpa command line options.
(mips_ases): Add MIPS XPA ASE.
(mips_cpu_info_table): Update p5600 entry to allow the XPA ASE.
* doc/as.texinfo: Document the MIPS XPA command line options.
* doc/c-mips.texi: Document the MIPS XPA command line options,
and assembler directives.
gas/testsuite/
* gas/mips/mips.exp: Add xpa tests.
* gas/mips/xpa.s: New test.
* gas/mips/xpa.d: Likewise.
include/
* opcode/mips.h (ASE_XPA): New define.
opcodes/
* mips-dis.c (mips_arch_choices): Update mips32r2 and mips64r2
to allow the MIPS XPA ASE.
(parse_mips_dis_option): Process the -Mxpa option.
* mips-opc.c (XPA): New define.
(mips_builtin_opcodes): Add MIPS XPA instructions and move the
locations of the ctc0 and cfc0 instructions.
Diffstat (limited to 'gas/config')
| -rw-r--r-- | gas/config/tc-mips.c | 15 |
1 files changed, 13 insertions, 2 deletions
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c index 47de8d3..960169e 100644 --- a/gas/config/tc-mips.c +++ b/gas/config/tc-mips.c @@ -1338,6 +1338,8 @@ enum options OPTION_NO_DSPR2, OPTION_EVA, OPTION_NO_EVA, + OPTION_XPA, + OPTION_NO_XPA, OPTION_MICROMIPS, OPTION_NO_MICROMIPS, OPTION_MCU, @@ -1447,6 +1449,8 @@ struct option md_longopts[] = {"mno-virt", no_argument, NULL, OPTION_NO_VIRT}, {"mmsa", no_argument, NULL, OPTION_MSA}, {"mno-msa", no_argument, NULL, OPTION_NO_MSA}, + {"mxpa", no_argument, NULL, OPTION_XPA}, + {"mno-xpa", no_argument, NULL, OPTION_NO_XPA}, /* Old-style architecture options. Don't add more of these. */ {"m4650", no_argument, NULL, OPTION_M4650}, @@ -1599,7 +1603,11 @@ static const struct mips_ase mips_ases[] = { { "msa", ASE_MSA, ASE_MSA64, OPTION_MSA, OPTION_NO_MSA, - 2, 2, 2, 2 } + 2, 2, 2, 2 }, + + { "xpa", ASE_XPA, 0, + OPTION_XPA, OPTION_NO_XPA, + 2, 2, -1, -1 } }; /* The set of ASEs that require -mfp64. */ @@ -17903,7 +17911,7 @@ static const struct mips_cpu_info mips_cpu_info_table[] = { "1004kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, { "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */ - { "p5600", 0, ASE_VIRT | ASE_EVA, ISA_MIPS32R2, CPU_MIPS32R2 }, + { "p5600", 0, ASE_VIRT | ASE_EVA | ASE_XPA, ISA_MIPS32R2, CPU_MIPS32R2 }, /* MIPS 64 */ { "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 }, @@ -18161,6 +18169,9 @@ MIPS options:\n\ -mmsa generate MSA instructions\n\ -mno-msa do not generate MSA instructions\n")); fprintf (stream, _("\ +-mxpa generate eXtended Physical Address (XPA) instructions\n\ +-mno-xpa do not generate eXtended Physical Address (XPA) instructions\n")); + fprintf (stream, _("\ -mvirt generate Virtualization instructions\n\ -mno-virt do not generate Virtualization instructions\n")); fprintf (stream, _("\ |