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| author | Andre Vieira <andre.simoesdiasvieira@arm.com> | 2019-05-15 16:52:50 +0100 |
|---|---|---|
| committer | Andre Vieira <andre.simoesdiasvieira@arm.com> | 2019-05-16 16:19:56 +0100 |
| commit | 485dee97c6431267b662b723eb092a6abfa4167c (patch) | |
| tree | cab930e1494cab890d7114f1364b97b6916a9346 /gas/config | |
| parent | 5ee9134313f9cce06d38144f5bc77c59e04df884 (diff) | |
| download | gdb-485dee97c6431267b662b723eb092a6abfa4167c.zip gdb-485dee97c6431267b662b723eb092a6abfa4167c.tar.gz gdb-485dee97c6431267b662b723eb092a6abfa4167c.tar.bz2 | |
[PATCH 3/57][Arm][GAS] Add support for MVE instructions: vabs and vneg
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (do_neon_abs_neg): Make it accept MVE variant.
(insns): Change vabs and vneg entries to accept MVE variants.
* testsuite/gas/arm/mve-vabsneg-bad-1.d: New test.
* testsuite/gas/arm/mve-vabsneg-bad-1.l: New test.
* testsuite/gas/arm/mve-vabsneg-bad-1.s: New test.
* testsuite/gas/arm/mve-vabsneg-bad-2.d: New test.
* testsuite/gas/arm/mve-vabsneg-bad-2.l: New test.
* testsuite/gas/arm/mve-vabsneg-bad-2.s: New test.
Diffstat (limited to 'gas/config')
| -rw-r--r-- | gas/config/tc-arm.c | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index 46d0f4e..8b1e9fc 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -15950,12 +15950,13 @@ do_neon_abs_neg (void) if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS) return; - if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) - return; - rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); et = neon_check_type (2, rs, N_EQK, N_S_32 | N_F_16_32 | N_KEY); + if (check_simd_pred_availability (et.type == NT_float, + NEON_CHECK_ARCH | NEON_CHECK_CC)) + return; + inst.instruction |= LOW4 (inst.operands[0].reg) << 12; inst.instruction |= HI1 (inst.operands[0].reg) << 22; inst.instruction |= LOW4 (inst.operands[1].reg); @@ -21909,9 +21910,6 @@ static const struct asm_opcode insns[] = nCEF(vmla, _vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar), nCEF(vmls, _vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar), - NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg), - NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg), - NCE(vldm, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), NCE(vldmia, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), NCE(vldmdb, d100b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), @@ -22643,6 +22641,9 @@ static const struct asm_opcode insns[] = mnCEF(vadd, _vadd, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQR), neon_addsub_if_i), mnCEF(vsub, _vsub, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQR), neon_addsub_if_i), + MNCEF(vabs, 1b10300, 2, (RNSDQMQ, RNSDQMQ), neon_abs_neg), + MNCEF(vneg, 1b10380, 2, (RNSDQMQ, RNSDQMQ), neon_abs_neg), + #undef ARM_VARIANT #define ARM_VARIANT & fpu_neon_ext_v1 mnUF(vabd, _vabd, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_if_su), |