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| author | Claire Xenia Wolf <claire@symbioticeda.com> | 2020-12-15 07:11:03 -0800 |
|---|---|---|
| committer | Nelson Chu <nelson.chu@sifive.com> | 2021-01-07 11:44:54 +0800 |
| commit | 2652cfad8d9d6ab05fe6296802ec499682a00749 (patch) | |
| tree | 117665ece17441b71841d299fa3cc151e38b4b9e /gas/config | |
| parent | d4e57b87a3d5879917c30e33b14760fd76ff7b38 (diff) | |
| download | gdb-2652cfad8d9d6ab05fe6296802ec499682a00749.zip gdb-2652cfad8d9d6ab05fe6296802ec499682a00749.tar.gz gdb-2652cfad8d9d6ab05fe6296802ec499682a00749.tar.bz2 | |
RISC-V: Support riscv bitmanip frozen ZBA/ZBB/ZBC instructions (v0.93).
In fact rev8/orc.b/zext.h are the aliases of grevi/gorci/pack[w], so we
should update them to INSN_ALIAS when we have supported their true instruction
in the future. Though we still use the [MATCH|MAKS]_[GREVI|GORCI|PACK|PACKW]
to encode them. Besides, the orc.b has the same encoding both in rv32 and
rv64, so we just keep one of them in the opcode table.
This patch is implemented according to the following link,
https://github.com/riscv/riscv-bitmanip/pull/101
2021-01-07 Claire Xenia Wolf <claire@symbioticeda.com>
Jim Wilson <jimw@sifive.com>
Andrew Waterman <andrew@sifive.com>
Maxim Blinov <maxim.blinov@embecosm.com>
Kito Cheng <kito.cheng@sifive.com>
Nelson Chu <nelson.chu@sifive.com>
bfd/
* elfxx-riscv.c (riscv_std_z_ext_strtab): Added zba, zbb and zbc.
gas/
* config/tc-riscv.c (riscv_multi_subset_supports): Handle INSN_CLASS_ZB*.
(riscv_get_default_ext_version): Do not check the default_isa_spec when
the version defined in the riscv_opcodes table is ISA_SPEC_CLASS_DRAFT.
* testsuite/gas/riscv/bitmanip-insns-32.d: New testcase.
* testsuite/gas/riscv/bitmanip-insns-64.d: Likewise.
* testsuite/gas/riscv/bitmanip-insns.s: Likewise.
include/
* opcode/riscv-opc.h: Added MASK/MATCH/DECLARE_INSN for ZBA/ZBB/ZBC.
* opcode/riscv.h (riscv_insn_class): Added INSN_CLASS_ZB*.
(enum riscv_isa_spec_class): Added ISA_SPEC_CLASS_DRAFT for the
frozen extensions.
opcodes/
* riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
(MASK_RVB_IMM): Used for rev8 and orc.b encoding.
Diffstat (limited to 'gas/config')
| -rw-r--r-- | gas/config/tc-riscv.c | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 55d5f1b..052199e 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -251,6 +251,16 @@ riscv_multi_subset_supports (enum riscv_insn_class insn_class) case INSN_CLASS_ZIFENCEI: return riscv_subset_supports ("zifencei"); + case INSN_CLASS_ZBA: + return riscv_subset_supports ("zba"); + case INSN_CLASS_ZBB: + return riscv_subset_supports ("zbb"); + case INSN_CLASS_ZBC: + return riscv_subset_supports ("zbc"); + case INSN_CLASS_ZBA_OR_ZBB: + return (riscv_subset_supports ("zba") + || riscv_subset_supports ("zbb")); + default: as_fatal ("Unreachable"); return FALSE; @@ -296,7 +306,8 @@ riscv_get_default_ext_version (const char *name, && ext->name && strcmp (ext->name, name) == 0) { - if (ext->isa_spec_class == default_isa_spec) + if (ext->isa_spec_class == ISA_SPEC_CLASS_DRAFT + || ext->isa_spec_class == default_isa_spec) { *major_version = ext->major_version; *minor_version = ext->minor_version; @@ -1454,6 +1465,7 @@ riscv_ext (int destreg, int srcreg, unsigned shift, bfd_boolean sign) } /* Expand RISC-V assembly macros into one or more instructions. */ + static void macro (struct riscv_cl_insn *ip, expressionS *imm_expr, bfd_reloc_code_real_type *imm_reloc) |