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| author | H.J. Lu <hjl.tools@gmail.com> | 2018-03-08 19:57:35 -0800 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2018-03-08 19:57:48 -0800 |
| commit | 0089daceaba4338046932e65a1b5882065416633 (patch) | |
| tree | 779e5859464843e858b513e0eedbec3c07c949a6 /gas/config | |
| parent | 567a3e54d211ab8d09119f99fed10b57db895450 (diff) | |
| download | gdb-0089daceaba4338046932e65a1b5882065416633.zip gdb-0089daceaba4338046932e65a1b5882065416633.tar.gz gdb-0089daceaba4338046932e65a1b5882065416633.tar.bz2 | |
x86: Optimize with EVEX128 encoding for AVX512VL
We can optimize AVX512 instructions with EVEX128 only if AVX512VL is
enabled:
1. Instruction is an AVX512VL instruction. Or
2. AVX512VL is enabled explicitly by -march=+avx512vl/".arch .avx512vl".
We should optimize EVEX instructions with EVEX128 encoding when pseudo
{evex} prefix is used.
* config/tc-i386.c (set_cpu_arch): Set cpu_arch_isa_flags.
(md_parse_option): Likewise.
(optimize_encoding): Check i.tm.cpu_flags and cpu_arch_isa_flags
for cpuavx512vl instead of cpu_arch_flags. Optimize EVEX with
EVEX128 when EVEX encoding is required.
* testsuite/gas/i386/i386.exp: Run optimize-4, optimize-5,
x86-64-optimize-5 and x86-64-optimize-6.
* testsuite/gas/i386/optimize-1.d: Updated.
* testsuite/gas/i386/x86-64-optimize-2.d: Likewise.
* testsuite/gas/i386/optimize-4.d: New file.
* testsuite/gas/i386/optimize-4.s: Likewise.
* testsuite/gas/i386/optimize-5.d: Likewise.
* testsuite/gas/i386/optimize-5.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-5.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-5.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-6.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-6.s: Likewise.
Diffstat (limited to 'gas/config')
| -rw-r--r-- | gas/config/tc-i386.c | 19 |
1 files changed, 11 insertions, 8 deletions
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 1c64d08..ef7b64b 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -2622,6 +2622,10 @@ set_cpu_arch (int dummy ATTRIBUTE_UNUSED) cpu_arch_flags = flags; cpu_arch_isa_flags = flags; } + else + cpu_arch_isa_flags + = cpu_flags_or (cpu_arch_isa_flags, + cpu_arch[j].flags); (void) restore_line_pointer (e); demand_empty_rest_of_line (); return; @@ -3871,7 +3875,8 @@ optimize_encoding (void) || (!i.mask && !i.rounding && is_evex_encoding (&i.tm) - && cpu_arch_flags.bitfield.cpuavx512vl)) + && (i.tm.cpu_flags.bitfield.cpuavx512vl + || cpu_arch_isa_flags.bitfield.cpuavx512vl))) && ((i.tm.base_opcode == 0x55 || i.tm.base_opcode == 0x6655 || i.tm.base_opcode == 0x66df @@ -3915,13 +3920,7 @@ optimize_encoding (void) */ if (is_evex_encoding (&i.tm)) { - /* If only lower 16 vector registers are used, we can use - VEX encoding. */ - for (j = 0; j < 3; j++) - if (register_number (i.op[j].regs) > 15) - break; - - if (j < 3) + if (i.vec_encoding == vex_encoding_evex) i.tm.opcode_modifier.evex = EVEX128; else { @@ -10524,6 +10523,10 @@ md_parse_option (int c, const char *arg) cpu_arch_flags = flags; cpu_arch_isa_flags = flags; } + else + cpu_arch_isa_flags + = cpu_flags_or (cpu_arch_isa_flags, + cpu_arch[j].flags); break; } } |