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| author | Jan Beulich <jbeulich@novell.com> | 2018-04-26 08:53:20 +0200 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2018-04-26 08:53:20 +0200 |
| commit | 7a69eac330adff3913a8698eac450cc7968ba8b0 (patch) | |
| tree | b18ae6062dbee55c24b75a279a83558f730dfec7 /gas/config | |
| parent | 1d3f82868db8881cd9ce79ad151fb0a7ebeb2c5a (diff) | |
| download | gdb-7a69eac330adff3913a8698eac450cc7968ba8b0.zip gdb-7a69eac330adff3913a8698eac450cc7968ba8b0.tar.gz gdb-7a69eac330adff3913a8698eac450cc7968ba8b0.tar.bz2 | |
x86: also optimize zeroing-masking variants of insns
When zeroing an element of a register it doesn't matter whether the zero
results from the actual operation (xor, sub, or nand) or from the
zeroing-masking taking effect due to a clear mask register bit.
Diffstat (limited to 'gas/config')
| -rw-r--r-- | gas/config/tc-i386.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index a48cfc2..6e0d1dd 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -3878,7 +3878,7 @@ optimize_encoding (void) && i.op[0].regs == i.op[1].regs && !i.types[2].bitfield.xmmword && (i.tm.opcode_modifier.vex - || (!i.mask + || ((!i.mask || i.mask->zeroing) && !i.rounding && is_evex_encoding (&i.tm) && (i.vec_encoding != vex_encoding_evex |