From 7a69eac330adff3913a8698eac450cc7968ba8b0 Mon Sep 17 00:00:00 2001 From: Jan Beulich Date: Thu, 26 Apr 2018 08:53:20 +0200 Subject: x86: also optimize zeroing-masking variants of insns When zeroing an element of a register it doesn't matter whether the zero results from the actual operation (xor, sub, or nand) or from the zeroing-masking taking effect due to a clear mask register bit. --- gas/config/tc-i386.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gas/config') diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index a48cfc2..6e0d1dd 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -3878,7 +3878,7 @@ optimize_encoding (void) && i.op[0].regs == i.op[1].regs && !i.types[2].bitfield.xmmword && (i.tm.opcode_modifier.vex - || (!i.mask + || ((!i.mask || i.mask->zeroing) && !i.rounding && is_evex_encoding (&i.tm) && (i.vec_encoding != vex_encoding_evex -- cgit v1.1