RISC-V: Add support for XCValu extension in CV32E40P

Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html

Contributors:
  Mary Bennett <mary.bennett@embecosm.com>
  Nandni Jamnadas <nandni.jamnadas@embecosm.com>
  Pietra Ferreira <pietra.ferreira@embecosm.com>
  Charlie Keaney
  Jessica Mills
  Craig Blackmore <craig.blackmore@embecosm.com>
  Simon Cook <simon.cook@embecosm.com>
  Jeremy Bennett <jeremy.bennett@embecosm.com>
  Helene Chelin <helene.chelin@embecosm.com>

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_multi_subset_supports): Added `xcvalu`
          instruction class.
	(riscv_multi_subset_supports_ext): Likewise.

gas/ChangeLog:

	* config/tc-riscv.c (validate_riscv_insn): Added the necessary
          operands for the extension.
	(riscv_ip): Likewise.
	* doc/c-riscv.texi: Noted XCValu as an additional ISA extension
          for CORE-V.
	* testsuite/gas/riscv/cv-alu-boundaries.d: New test.
	* testsuite/gas/riscv/cv-alu-boundaries.l: New test.
	* testsuite/gas/riscv/cv-alu-boundaries.s: New test.
	* testsuite/gas/riscv/cv-alu-fail-march.d: New test.
	* testsuite/gas/riscv/cv-alu-fail-march.l: New test.
	* testsuite/gas/riscv/cv-alu-fail-march.s: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-01.d: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-01.l: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-01.s: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-02.d: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-02.l: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-02.s: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-03.d: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-03.l: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-03.s: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-04.d: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-04.l: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-04.s: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-05.d: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-05.l: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-05.s: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-06.d: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-06.l: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-06.s: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-07.d: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-07.l: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-07.s: New test.
	* testsuite/gas/riscv/cv-alu-insns.d: New test.
	* testsuite/gas/riscv/cv-alu-insns.s: New test.

opcodes/ChangeLog:

	* riscv-dis.c (print_insn_args): Disassemble xcb operand.
	* riscv-opc.c: Defined the MASK and added XCValu instructions.

include/ChangeLog:

	* opcode/riscv-opc.h: Added corresponding MATCH and MASK macros
          for XCValu.
	* opcode/riscv.h: Added corresponding EXTRACT and ENCODE macros
          for XCValu.
	(enum riscv_insn_class): Added the XCValu instruction class.

1 files changed, 14 insertions, 0 deletions

diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 29676bc..402c46a 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -1484,6 +1484,10 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
 	    case 'c': /* Vendor-specific (CORE-V) operands.  */
 	      switch (*++oparg)
 		{
+		  case '2':
+		    /* ls2[4:0] */
+		    used_bits |= ENCODE_CV_IS2_UIMM5 (-1U);
+		    break;
 		  case '3':
 		    used_bits |= ENCODE_CV_IS3_UIMM5 (-1U);
 		    break;
@@ -3594,6 +3598,16 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
 		case 'c': /* Vendor-specific (CORE-V) operands.  */
 		  switch (*++oparg)
 		    {
+		      case '2':
+			my_getExpression (imm_expr, asarg);
+			check_absolute_expr (ip, imm_expr, FALSE);
+			asarg = expr_parse_end;
+			if (imm_expr->X_add_number<0
+			    || imm_expr->X_add_number>31)
+			  break;
+			ip->insn_opcode
+			    |= ENCODE_CV_IS2_UIMM5 (imm_expr->X_add_number);
+			  continue;
 		      case '3':
 			my_getExpression (imm_expr, asarg);
 			check_absolute_expr (ip, imm_expr, FALSE);