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| author | Jiawei <jiawei@iscas.ac.cn> | 2024-06-11 21:59:00 +0800 |
|---|---|---|
| committer | Nelson Chu <nelson@rivosinc.com> | 2024-06-12 08:47:19 +0800 |
| commit | b7641ae1afaa39e31e70114f0ee9a295820709aa (patch) | |
| tree | e01560828128115c52b90614ef7cf0e60a34d446 /gas/config/tc-riscv.c | |
| parent | a3d147a45447c4431ea66dd37911ac9415cb4fd8 (diff) | |
| download | gdb-b7641ae1afaa39e31e70114f0ee9a295820709aa.zip gdb-b7641ae1afaa39e31e70114f0ee9a295820709aa.tar.gz gdb-b7641ae1afaa39e31e70114f0ee9a295820709aa.tar.bz2 | |
RISC-V: Support S[sm]csrind extension csrs.
This patch supports RISC-V Smcsrind/Sscsrind privilege extension csrs.
Reuse csr 'smselect/siselect', 'mireg/sireg' and 'vsiselect,vsireg' csrs
in Smaia/Ssaia extension.
bfd/ChangeLog:
* elfxx-riscv.c: New extensions.
gas/ChangeLog:
* NEWS: Updated.
* config/tc-riscv.c (enum riscv_csr_class): New extensions.
(riscv_csr_address): Ditto.
* testsuite/gas/riscv/csr-version-1p10.d: New csrs.
* testsuite/gas/riscv/csr-version-1p10.l: Ditto.
* testsuite/gas/riscv/csr-version-1p11.d: Ditto.
* testsuite/gas/riscv/csr-version-1p11.l: Ditto.
* testsuite/gas/riscv/csr-version-1p12.d: Ditto.
* testsuite/gas/riscv/csr-version-1p12.l: Ditto.
* testsuite/gas/riscv/csr.s: Ditto.
* testsuite/gas/riscv/march-help.l: New extensions.
include/ChangeLog:
* opcode/riscv-opc.h (CSR_MIREG2): New csr.
(CSR_MIREG3): Ditto.
(CSR_MIREG4): Ditto.
(CSR_MIREG5): Ditto.
(CSR_MIREG6): Ditto.
(CSR_SIREG2): Ditto.
(CSR_SIREG3): Ditto.
(CSR_SIREG4): Ditto.
(CSR_SIREG5): Ditto.
(CSR_SIREG6): Ditto.
(CSR_VSIREG2): Ditto.
(CSR_VSIREG3): Ditto.
(CSR_VSIREG4): Ditto.
(CSR_VSIREG5): Ditto.
(CSR_VSIREG6): Ditto.
(DECLARE_CSR): Ditto.
Diffstat (limited to 'gas/config/tc-riscv.c')
| -rw-r--r-- | gas/config/tc-riscv.c | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index ccc073a..e008370 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -77,6 +77,8 @@ enum riscv_csr_class CSR_CLASS_H_32, /* hypervisor, rv32 only */ CSR_CLASS_SMAIA, /* Smaia */ CSR_CLASS_SMAIA_32, /* Smaia, rv32 only */ + CSR_CLASS_SMAIA_OR_SMCSRIND, /* Smaia/Smcsrind */ + CSR_CLASS_SMCSRIND, /* Smcsrind */ CSR_CLASS_SMCNTRPMF, /* Smcntrpmf */ CSR_CLASS_SMCNTRPMF_32, /* Smcntrpmf, rv32 only */ CSR_CLASS_SMSTATEEN, /* Smstateen only */ @@ -85,6 +87,10 @@ enum riscv_csr_class CSR_CLASS_SSAIA_AND_H, /* Ssaia with H */ CSR_CLASS_SSAIA_32, /* Ssaia, rv32 only */ CSR_CLASS_SSAIA_AND_H_32, /* Ssaia with H, rv32 only */ + CSR_CLASS_SSAIA_OR_SSCSRIND, /* Ssaia/Smcsrind */ + CSR_CLASS_SSAIA_OR_SSCSRIND_AND_H, /* Ssaia/Smcsrind with H */ + CSR_CLASS_SSCSRIND, /* Sscsrind */ + CSR_CLASS_SSCSRIND_AND_H, /* Sscsrind with H */ CSR_CLASS_SSSTATEEN, /* S[ms]stateen only */ CSR_CLASS_SSSTATEEN_AND_H, /* S[ms]stateen only (with H) */ CSR_CLASS_SSSTATEEN_AND_H_32, /* S[ms]stateen RV32 only (with H) */ @@ -1059,6 +1065,12 @@ riscv_csr_address (const char *csr_name, case CSR_CLASS_SMAIA: extension = "smaia"; break; + case CSR_CLASS_SMAIA_OR_SMCSRIND: + extension = "smaia or smcsrind"; + break; + case CSR_CLASS_SMCSRIND: + extension = "smcsrind"; + break; case CSR_CLASS_SMCNTRPMF_32: is_rv32_only = true; /* Fall through. */ @@ -1082,6 +1094,16 @@ riscv_csr_address (const char *csr_name, || csr_class == CSR_CLASS_SSAIA_AND_H_32); extension = "ssaia"; break; + case CSR_CLASS_SSAIA_OR_SSCSRIND: + case CSR_CLASS_SSAIA_OR_SSCSRIND_AND_H: + is_h_required = (csr_class == CSR_CLASS_SSAIA_OR_SSCSRIND_AND_H); + extension = "ssaia or sscsrind"; + break; + case CSR_CLASS_SSCSRIND: + case CSR_CLASS_SSCSRIND_AND_H: + is_h_required = (csr_class == CSR_CLASS_SSCSRIND_AND_H); + extension = "sscsrind"; + break; case CSR_CLASS_SSSTATEEN_AND_H_32: is_rv32_only = true; /* Fall through. */ |