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| author | H.J. Lu <hjl.tools@gmail.com> | 2008-08-28 14:07:50 +0000 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2008-08-28 14:07:50 +0000 |
| commit | 1ca35711f453e9a18d2a23795fc4305ace8eb1d4 (patch) | |
| tree | c575781b0204098113db0a6478b59342b77d7f8b /gas/config/tc-ia64.c | |
| parent | b29d32ce5c7f783e1df1f0bf63245c8614e939f6 (diff) | |
| download | gdb-1ca35711f453e9a18d2a23795fc4305ace8eb1d4.zip gdb-1ca35711f453e9a18d2a23795fc4305ace8eb1d4.tar.gz gdb-1ca35711f453e9a18d2a23795fc4305ace8eb1d4.tar.bz2 | |
gas/
2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-ia64.c (CR_IIB0): New.
(CR_IIB1): Likewise.
(cr): Add cr.iib0 and cr.iib1.
(specify_resource): Handle IA64_RS_CR_IIB and CR_IIB0/CR_IIB1.
gas/testsuite/
2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
* gas/ia64/dv-raw-err.s: Add tests for cr.iib0 and cr.iib1.
* gas/ia64/dv-waw-err.s: Likewise.
* gas/ia64/regs.s: Likewise.
* gas/ia64/dv-raw-err.l: Updated.
* gas/ia64/dv-waw-err.l: Likewise.
* gas/ia64/regs.d: Likewise.
include/opcode/
2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
* ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
IA64_RS_CR.
opcodes/
2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
* ia64-dis.c (print_insn_ia64): Handle cr.iib0 and cr.iib1.
* ia64-gen.c (lookup_specifier): Likewise.
* ia64-ic.tbl: Add support for cr.iib0 and cr.iib1.
* ia64-raw.tbl: Likewise.
* ia64-waw.tbl: Likewise.
* ia64-asmtab.c: Regenerated.
Diffstat (limited to 'gas/config/tc-ia64.c')
| -rw-r--r-- | gas/config/tc-ia64.c | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/gas/config/tc-ia64.c b/gas/config/tc-ia64.c index e31bd26..da56dd3 100644 --- a/gas/config/tc-ia64.c +++ b/gas/config/tc-ia64.c @@ -408,6 +408,8 @@ ar[] = #define CR_IFS 23 #define CR_IIM 24 #define CR_IHA 25 +#define CR_IIB0 26 +#define CR_IIB1 27 #define CR_LID 64 #define CR_IVR 65 #define CR_TPR 66 @@ -441,6 +443,8 @@ cr[] = {"cr.ifs", CR_IFS}, {"cr.iim", CR_IIM}, {"cr.iha", CR_IHA}, + {"cr.iib0", CR_IIB0}, + {"cr.iib1", CR_IIB1}, {"cr.lid", CR_LID}, {"cr.ivr", CR_IVR}, {"cr.tpr", CR_TPR}, @@ -8417,6 +8421,23 @@ dep->name, idesc->name, (rsrc_write?"write":"read"), note) } break; + case IA64_RS_CR_IIB: + if (note != 0) + { + UNHANDLED; + } + else + { + int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR; + if (idesc->operands[!rsrc_write] == IA64_OPND_CR3 + && (regno == CR_IIB0 || regno == CR_IIB1)) + { + specs[count] = tmpl; + specs[count++].index = regno; + } + } + break; + case IA64_RS_CR_LRR: if (note != 1) { @@ -8848,6 +8869,8 @@ dep->name, idesc->name, (rsrc_write?"write":"read"), note) case CR_ISR: case CR_IFA: case CR_IHA: + case CR_IIB0: + case CR_IIB1: case CR_IIPA: specs[count++] = tmpl; break; |