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| author | Jan Beulich <jbeulich@suse.com> | 2021-03-25 08:18:41 +0100 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2021-03-25 08:18:41 +0100 |
| commit | c0e54661f755b1eb1cbf745bc4eb4a068cd5ada2 (patch) | |
| tree | 15a8fd41581bb0ac66ff93e9b22f947a022ebf0d /gas/config/tc-i386.c | |
| parent | 829f3fe1f0230798c776b9c7039fa7be778a7b43 (diff) | |
| download | gdb-c0e54661f755b1eb1cbf745bc4eb4a068cd5ada2.zip gdb-c0e54661f755b1eb1cbf745bc4eb4a068cd5ada2.tar.gz gdb-c0e54661f755b1eb1cbf745bc4eb4a068cd5ada2.tar.bz2 | |
x86: fix AMD Zen3 insns
For INVLPGB the operand count was wrong (besides %edx there's also %ecx
which is an input to the insn). In this case I see little sense in
retaining the bogus 2-operand template. Plus swapping of the operands
wasn't properly suppressed for Intel syntax.
For PVALIDATE, RMPADJUST, and RMPUPDATE bogus single operand templates
were specified. These get retained, as the address operand is the only
one really needed to expressed non-default address size, but only for
compatibility reasons. Proper multi-operand insn get introduced and the
testcases get adjusted / extended accordingly.
While at it also drop the redundant definition of __amd64__ - we already
have x86_64 defined (or not) to distinguish 64-bit and non-64-bit cases.
Diffstat (limited to 'gas/config/tc-i386.c')
| -rw-r--r-- | gas/config/tc-i386.c | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index c2c5b69..785d0c4 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -4679,16 +4679,18 @@ md_assemble (char *line) operands at hand. */ /* All Intel opcodes have reversed operands except for "bound", "enter", - "monitor*", "mwait*", "tpause", and "umwait". We also don't reverse - intersegment "jmp" and "call" instructions with 2 immediate operands so - that the immediate segment precedes the offset, as it does when in AT&T - mode. */ + "invlpg*", "monitor*", "mwait*", "tpause", "umwait", "pvalidate", + "rmpadjust", and "rmpupdate". We also don't reverse intersegment "jmp" + and "call" instructions with 2 immediate operands so that the immediate + segment precedes the offset consistently in Intel and AT&T modes. */ if (intel_syntax && i.operands > 1 && (strcmp (mnemonic, "bound") != 0) - && (strcmp (mnemonic, "invlpga") != 0) + && (strncmp (mnemonic, "invlpg", 6) != 0) && (strncmp (mnemonic, "monitor", 7) != 0) && (strncmp (mnemonic, "mwait", 5) != 0) + && (strcmp (mnemonic, "pvalidate") != 0) + && (strncmp (mnemonic, "rmp", 3) != 0) && (strcmp (mnemonic, "tpause") != 0) && (strcmp (mnemonic, "umwait") != 0) && !(operand_type_check (i.types[0], imm) |