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| author | Jan Beulich <jbeulich@suse.com> | 2021-03-29 12:02:50 +0200 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2021-03-29 12:02:50 +0200 |
| commit | 389d00a5e5b1fa6fcd9eda747b17ef73f58eb693 (patch) | |
| tree | 60328fd218e7998c30d91455df475d835272214e /gas/config/tc-i386-intel.c | |
| parent | 63b4cc53dc41c755f8b30d85edf29c153f76eba3 (diff) | |
| download | gdb-389d00a5e5b1fa6fcd9eda747b17ef73f58eb693.zip gdb-389d00a5e5b1fa6fcd9eda747b17ef73f58eb693.tar.gz gdb-389d00a5e5b1fa6fcd9eda747b17ef73f58eb693.tar.bz2 | |
x86: derive opcode encoding space attribute from base opcode
Just like is already done for VEX/XOP/EVEX encoded insns, record the
encoding space information in the respective opcode modifier field. Do
this again without changing the source table, but rather by deriving the
values from their existing source representation.
Diffstat (limited to 'gas/config/tc-i386-intel.c')
| -rw-r--r-- | gas/config/tc-i386-intel.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/gas/config/tc-i386-intel.c b/gas/config/tc-i386-intel.c index 9b7f429..4c9f0b7 100644 --- a/gas/config/tc-i386-intel.c +++ b/gas/config/tc-i386-intel.c @@ -318,9 +318,11 @@ i386_intel_simplify_register (expressionS *e) if (intel_state.in_scale || (t->opcode_modifier.opcodeprefix == PREFIX_0XF3 - && t->base_opcode == 0x0f1b /* bndmk */) + && t->opcode_modifier.opcodespace == SPACE_0F + && t->base_opcode == 0x1b /* bndmk */) || (t->opcode_modifier.opcodeprefix == PREFIX_NONE - && (t->base_opcode & ~1) == 0x0f1a /* bnd{ld,st}x */) + && t->opcode_modifier.opcodespace == SPACE_0F + && (t->base_opcode & ~1) == 0x1a /* bnd{ld,st}x */) || i386_regtab[reg_num].reg_type.bitfield.baseindex) intel_state.index = i386_regtab + reg_num; else |