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| author | Sudakshina Das <sudi.das@arm.com> | 2018-09-26 10:52:51 +0100 |
|---|---|---|
| committer | Richard Earnshaw <Richard.Earnshaw@arm.com> | 2018-10-09 15:17:10 +0100 |
| commit | 2ac435d46608be7ef90f80aaf9ff48443aea571e (patch) | |
| tree | 9adf96d34751880e859e59074696a51b5b8debc4 /gas/config/tc-aarch64.c | |
| parent | 68dfbb92ef5f013a315d652c88ede2082c16a88e (diff) | |
| download | gdb-2ac435d46608be7ef90f80aaf9ff48443aea571e.zip gdb-2ac435d46608be7ef90f80aaf9ff48443aea571e.tar.gz gdb-2ac435d46608be7ef90f80aaf9ff48443aea571e.tar.bz2 | |
[PATCH, BINUTILS, AARCH64, 4/9] Add Execution and Data Restriction instructions
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order)
This patch adds the prediction restriction instructions (that is, cfp,
dvp, cpp). These instructions are retrospectively made optional for
all versions of the architecture from ARMv8.0 to ARMv8.4 and is
mandatory from ARMv8.5. Hence adding a new +predres which can be used
by the older architectures.
*** include/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_PREDRES): New.
(AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_PREDRES by default.
(aarch64_opnd): Add AARCH64_OPND_SYSREG_SR.
(aarch64_sys_regs_sr): Declare new table.
*** opcodes/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-dis.c (aarch64_ext_sysins_op): Add case for
AARCH64_OPND_SYSREG_SR.
* aarch64-opc.c (aarch64_print_operand): Likewise.
(aarch64_sys_regs_sr): Define table.
(aarch64_sys_ins_reg_supported_p): Check for RCTX with
AARCH64_FEATURE_PREDRES.
* aarch64-tbl.h (aarch64_feature_predres): New.
(PREDRES, PREDRES_INSN): New.
(aarch64_opcode_table): Add entries for cfp, dvp and cpp.
(AARCH64_OPERANDS): Add new description for SYSREG_SR.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
*** gas/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (aarch64_sys_regs_sr_hsh): New.
(parse_operands): Add entry for AARCH64_OPND_SYSREG_SR.
(md_begin): Allocate and initialize aarch64_sys_regs_sr_hsh
with aarch64_sys_regs_sr.
(aarch64_features): Add new "predres" option for older
architectures.
* doc/c-aarch64.texi: Document the same.
* testsuite/gas/aarch64/sysreg-4.s: New.
* testsuite/gas/aarch64/sysreg-4.d: New.
* testsuite/gas/aarch64/illegal-sysreg-4.d: New.
* testsuite/gas/aarch64/illegal-sysreg-4.l: New.
* testsuite/gas/aarch64/predres.s: New.
* testsuite/gas/aarch64/predres.d: New.
Diffstat (limited to 'gas/config/tc-aarch64.c')
| -rw-r--r-- | gas/config/tc-aarch64.c | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 045ad52..8621a33 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -462,6 +462,7 @@ static struct hash_control *aarch64_sys_regs_ic_hsh; static struct hash_control *aarch64_sys_regs_dc_hsh; static struct hash_control *aarch64_sys_regs_at_hsh; static struct hash_control *aarch64_sys_regs_tlbi_hsh; +static struct hash_control *aarch64_sys_regs_sr_hsh; static struct hash_control *aarch64_reg_hsh; static struct hash_control *aarch64_barrier_opt_hsh; static struct hash_control *aarch64_nzcv_hsh; @@ -6422,14 +6423,22 @@ parse_operands (char *str, const aarch64_opcode *opcode) inst.base.operands[i].sysins_op = parse_sys_ins_reg (&str, aarch64_sys_regs_ic_hsh); goto sys_reg_ins; + case AARCH64_OPND_SYSREG_DC: inst.base.operands[i].sysins_op = parse_sys_ins_reg (&str, aarch64_sys_regs_dc_hsh); goto sys_reg_ins; + case AARCH64_OPND_SYSREG_AT: inst.base.operands[i].sysins_op = parse_sys_ins_reg (&str, aarch64_sys_regs_at_hsh); goto sys_reg_ins; + + case AARCH64_OPND_SYSREG_SR: + inst.base.operands[i].sysins_op = + parse_sys_ins_reg (&str, aarch64_sys_regs_sr_hsh); + goto sys_reg_ins; + case AARCH64_OPND_SYSREG_TLBI: inst.base.operands[i].sysins_op = parse_sys_ins_reg (&str, aarch64_sys_regs_tlbi_hsh); @@ -8439,6 +8448,7 @@ md_begin (void) || (aarch64_sys_regs_dc_hsh = hash_new ()) == NULL || (aarch64_sys_regs_at_hsh = hash_new ()) == NULL || (aarch64_sys_regs_tlbi_hsh = hash_new ()) == NULL + || (aarch64_sys_regs_sr_hsh = hash_new ()) == NULL || (aarch64_reg_hsh = hash_new ()) == NULL || (aarch64_barrier_opt_hsh = hash_new ()) == NULL || (aarch64_nzcv_hsh = hash_new ()) == NULL @@ -8477,6 +8487,11 @@ md_begin (void) aarch64_sys_regs_tlbi[i].name, (void *) (aarch64_sys_regs_tlbi + i)); + for (i = 0; aarch64_sys_regs_sr[i].name != NULL; i++) + checked_hash_insert (aarch64_sys_regs_sr_hsh, + aarch64_sys_regs_sr[i].name, + (void *) (aarch64_sys_regs_sr + i)); + for (i = 0; i < ARRAY_SIZE (reg_names); i++) checked_hash_insert (aarch64_reg_hsh, reg_names[i].name, (void *) (reg_names + i)); @@ -8749,6 +8764,8 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = { AARCH64_ARCH_NONE}, {"sb", AARCH64_FEATURE (AARCH64_FEATURE_SB, 0), AARCH64_ARCH_NONE}, + {"predres", AARCH64_FEATURE (AARCH64_FEATURE_PREDRES, 0), + AARCH64_ARCH_NONE}, {"aes", AARCH64_FEATURE (AARCH64_FEATURE_AES, 0), AARCH64_ARCH_NONE}, {"sm4", AARCH64_FEATURE (AARCH64_FEATURE_SM4, 0), |