strip trailing whitespace in Blackfin files

1 files changed, 74 insertions, 74 deletions

diff --git a/gas/config/bfin-parse.y b/gas/config/bfin-parse.y
index fa06f61..2d569e2 100644
--- a/gas/config/bfin-parse.y
+++ b/gas/config/bfin-parse.y
@@ -170,7 +170,7 @@ void error (char *format, ...)
 {
     va_list ap;
     static char buffer[2000];
-    
+
     va_start (ap, format);
     vsprintf (buffer, format, ap);
     va_end (ap);
@@ -297,7 +297,7 @@ check_macfuncs (Macfunc *aa, Opt_mode *opa,
     return yyerror ("Bad opt mode");
 
   /* If a0macfunc comes before a1macfunc, swap them.  */
-	
+
   if (aa->n == 0)
     {
       /*  (M) is not allowed here.  */
@@ -353,7 +353,7 @@ check_macfuncs (Macfunc *aa, Opt_mode *opa,
   /* Make sure first macfunc has got both P flags ORed.  */
   aa->P |= ab->P;
 
-  return 0;	
+  return 0;
 }
 
 
@@ -478,7 +478,7 @@ dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported");
 %token SHIFT LSHIFT ASHIFT BXORSHIFT
 %token _GREATER_GREATER_GREATER_THAN_ASSIGN
 %token ROT
-%token LESS_LESS GREATER_GREATER  
+%token LESS_LESS GREATER_GREATER
 %token _GREATER_GREATER_GREATER
 %token _LESS_LESS_ASSIGN _GREATER_GREATER_ASSIGN
 %token DIVS DIVQ
@@ -545,7 +545,7 @@ dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported");
 %type <reg> a_plusassign
 %type <reg> a_minusassign
 %type <macfunc> multiply_halfregs
-%type <macfunc> assign_macfunc 
+%type <macfunc> assign_macfunc
 %type <macfunc> a_macfunc
 %type <expr> expr_1
 %type <instr> asm_1
@@ -566,11 +566,11 @@ dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported");
 %type <reg> REG_A_DOUBLE_ZERO
 %type <reg> REG_A_DOUBLE_ONE
 %type <reg> REG_A
-%type <reg> STATUS_REG 
+%type <reg> STATUS_REG
 %type <expr> expr
 %type <r0> xpmod
 %type <r0> xpmod1
-%type <modcodes> smod 
+%type <modcodes> smod
 %type <modcodes> b3_op
 %type <modcodes> rnd_op
 %type <modcodes> post_op
@@ -605,7 +605,7 @@ dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported");
 %right TILDA BANG
 %start statement
 %%
-statement: 
+statement:
 	| asm
 	{
 	  insn = $1;
@@ -690,7 +690,7 @@ asm: asm_1 SEMICOLON
 
 /* DSPMAC.  */
 
-asm_1:   
+asm_1:
 	MNOP
 	{
 	  $$ = DSP32MAC (3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0);
@@ -706,7 +706,7 @@ asm_1:
 
 	  if ($1.n == 0)
 	    {
-	      if ($2.MM) 
+	      if ($2.MM)
 		return yyerror ("(m) not allowed with a0 unit");
 	      op1 = 3;
 	      op0 = $1.op;
@@ -737,7 +737,7 @@ asm_1:
 	{
 	  Register *dst;
 
-	  if (check_macfuncs (&$1, &$2, &$4, &$5) < 0) 
+	  if (check_macfuncs (&$1, &$2, &$4, &$5) < 0)
 	    return -1;
 	  notethat ("assign_macfunc (.), assign_macfunc (.)\n");
 
@@ -765,9 +765,9 @@ asm_1:
 	      notethat ("dsp32alu: dregs = ( A0 += A1 )\n");
 	      $$ = DSP32ALU (11, 0, 0, &$1, 0, 0, 0, 0, 0);
 	    }
-	  else 
+	  else
 	    return yyerror ("Register mismatch");
-	}	
+	}
 	| HALF_REG ASSIGN LPAREN a_plusassign REG_A RPAREN
 	{
 	  if (!IS_A1 ($4) && IS_A1 ($5))
@@ -805,7 +805,7 @@ asm_1:
 	}
 
 	| LPAREN REG COMMA REG RPAREN ASSIGN BYTEOP16M LPAREN REG COLON expr COMMA
-	  REG COLON expr RPAREN aligndir 
+	  REG COLON expr RPAREN aligndir
 	{
 	  if (!IS_DREG ($2) || !IS_DREG ($4))
 	    return yyerror ("Dregs expected");
@@ -855,14 +855,14 @@ asm_1:
 	}
 
 
-	| REG ASSIGN REG_A PLUS REG_A COMMA REG ASSIGN REG_A MINUS REG_A amod1 
+	| REG ASSIGN REG_A PLUS REG_A COMMA REG ASSIGN REG_A MINUS REG_A amod1
 	{
 	  if (IS_DREG ($1) && IS_DREG ($7) && !REG_SAME ($3, $5)
 	      && IS_A1 ($9) && !IS_A1 ($11))
 	    {
 	      notethat ("dsp32alu: dregs = A1 + A0 , dregs = A1 - A0 (amod1)\n");
 	      $$ = DSP32ALU (17, 0, &$1, &$7, 0, 0, $12.s0, $12.x0, 0);
-	      
+
 	    }
 	  else if (IS_DREG ($1) && IS_DREG ($7) && !REG_SAME ($3, $5)
 		   && !IS_A1 ($9) && IS_A1 ($11))
@@ -876,7 +876,7 @@ asm_1:
 
 	| REG ASSIGN REG plus_minus REG COMMA REG ASSIGN REG plus_minus REG amod1
 	{
-	  if ($4.r0 == $10.r0) 
+	  if ($4.r0 == $10.r0)
 	    return yyerror ("Operators must differ");
 
 	  if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5)
@@ -892,15 +892,15 @@ asm_1:
 
 /*  Bar Operations.  */
 
-	| REG ASSIGN REG op_bar_op REG COMMA REG ASSIGN REG op_bar_op REG amod2 
+	| REG ASSIGN REG op_bar_op REG COMMA REG ASSIGN REG op_bar_op REG amod2
 	{
 	  if (!REG_SAME ($3, $9) || !REG_SAME ($5, $11))
 	    return yyerror ("Differing source registers");
 
-	  if (!IS_DREG ($1) || !IS_DREG ($3) || !IS_DREG ($5) || !IS_DREG ($7)) 
+	  if (!IS_DREG ($1) || !IS_DREG ($3) || !IS_DREG ($5) || !IS_DREG ($7))
 	    return yyerror ("Dregs expected");
 
-	
+
 	  if ($4.r0 == 1 && $10.r0 == 2)
 	    {
 	      notethat ("dsp32alu:  dregs = dregs .|. dregs , dregs = dregs .|. dregs (amod2)\n");
@@ -1063,7 +1063,7 @@ asm_1:
 	}
 
 	| HALF_REG ASSIGN HALF_REG ASSIGN SIGN LPAREN HALF_REG RPAREN STAR
-	  HALF_REG PLUS SIGN LPAREN HALF_REG RPAREN STAR HALF_REG 
+	  HALF_REG PLUS SIGN LPAREN HALF_REG RPAREN STAR HALF_REG
 	{
 	  if (IS_HCOMPL ($1, $3) && IS_HCOMPL ($7, $14) && IS_HCOMPL ($10, $17))
 	    {
@@ -1076,7 +1076,7 @@ asm_1:
 	  else
 	    return yyerror ("Dregs expected");
 	}
-	| REG ASSIGN REG plus_minus REG amod1 
+	| REG ASSIGN REG plus_minus REG amod1
 	{
 	  if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
 	    {
@@ -1187,7 +1187,7 @@ asm_1:
 	    return yyerror ("Dregs expected");
 	}
 
-	| a_assign REG_A 
+	| a_assign REG_A
 	{
 	  if (!REG_SAME ($1, $2))
 	    {
@@ -1288,7 +1288,7 @@ asm_1:
 		  notethat ("LDIMMhalf: regs = luimm16 (x)\n");
 		  /* reg, H, S, Z.   */
 		  $$ = LDIMMHALF_R5 (&$1, 0, 1, 0, $3);
-		} 
+		}
 	    }
 	  else
 	    {
@@ -1323,7 +1323,7 @@ asm_1:
 	    return yyerror ("Register mismatch");
 	}
 
-	| REG ASSIGN REG op_bar_op REG amod0 
+	| REG ASSIGN REG op_bar_op REG amod0
 	{
 	  if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
 	    {
@@ -1554,7 +1554,7 @@ asm_1:
 	  else
 	    return yyerror ("Register mismatch");
 	}
-			
+
 /*  COMP3 CCFLAG.  */
 	| REG ASSIGN REG BAR REG
 	{
@@ -1766,7 +1766,7 @@ asm_1:
 	  notethat ("CC2dreg: CC =! CC\n");
 	  $$ = bfin_gen_cc2dreg (3, 0);
 	}
-			
+
 /* DSPMULT.  */
 
 	| HALF_REG ASSIGN multiply_halfregs opt_mode
@@ -1790,12 +1790,12 @@ asm_1:
 	  else
 	    {
 	      $$ = DSP32MULT (0, 0, $4.mod, 0, 0,
-			      0, 0, IS_H ($3.s0), IS_H ($3.s1), 
+			      0, 0, IS_H ($3.s0), IS_H ($3.s1),
 			      &$1, 0, &$3.s0, &$3.s1, 1);
 	    }
 	}
 
-	| REG ASSIGN multiply_halfregs opt_mode 
+	| REG ASSIGN multiply_halfregs opt_mode
 	{
 	  /* Odd registers can use (M).  */
 	  if (!IS_DREG ($1))
@@ -1820,7 +1820,7 @@ asm_1:
 	    {
 	      notethat ("dsp32mult: dregs = multiply_halfregs opt_mode\n");
 	      $$ = DSP32MULT (0, 0, $4.mod, 0, 1,
-			      0, 0, IS_H ($3.s0), IS_H ($3.s1), 
+			      0, 0, IS_H ($3.s0), IS_H ($3.s1),
 			      &$1,  0, &$3.s0, &$3.s1, 1);
 	    }
 	}
@@ -1828,7 +1828,7 @@ asm_1:
 	| HALF_REG ASSIGN multiply_halfregs opt_mode COMMA
           HALF_REG ASSIGN multiply_halfregs opt_mode
 	{
-	  if (!IS_DREG ($1) || !IS_DREG ($6)) 
+	  if (!IS_DREG ($1) || !IS_DREG ($6))
 	    return yyerror ("Dregs expected");
 
 	  if (!IS_HCOMPL($1, $6))
@@ -1856,7 +1856,7 @@ asm_1:
 
 	| REG ASSIGN multiply_halfregs opt_mode COMMA REG ASSIGN multiply_halfregs opt_mode
 	{
-	  if (!IS_DREG ($1) || !IS_DREG ($6)) 
+	  if (!IS_DREG ($1) || !IS_DREG ($6))
 	    return yyerror ("Dregs expected");
 
 	  if ((IS_EVEN ($1) && $6.regno - $1.regno != 1)
@@ -1958,7 +1958,7 @@ asm_1:
 	  else
 	    return yyerror ("Bad shift value or register");
 	}
-	| HALF_REG ASSIGN HALF_REG LESS_LESS expr smod 
+	| HALF_REG ASSIGN HALF_REG LESS_LESS expr smod
 	{
 	  if (IS_UIMM ($5, 4))
 	    {
@@ -1990,7 +1990,7 @@ asm_1:
 		}
 	      else
 		{
-		  
+
 		  op = 2;
 		  notethat ("dsp32shift: dregs = ASHIFT dregs BY dregs_lo (.)\n");
 		}
@@ -2053,7 +2053,7 @@ asm_1:
 	    return yyerror ("Register mismatch");
 	}
 
-	| REG ASSIGN EXTRACT LPAREN REG COMMA HALF_REG RPAREN xpmod 
+	| REG ASSIGN EXTRACT LPAREN REG COMMA HALF_REG RPAREN xpmod
 	{
 	  if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG_L ($7))
 	    {
@@ -2230,7 +2230,7 @@ asm_1:
 	    return yyerror ("Register mismatch");
 	}
 
-	| HALF_REG ASSIGN CCREG ASSIGN BXORSHIFT LPAREN REG_A COMMA REG RPAREN 
+	| HALF_REG ASSIGN CCREG ASSIGN BXORSHIFT LPAREN REG_A COMMA REG RPAREN
 	{
 	  if (IS_DREG ($1)
 	      && $7.regno == REG_A0
@@ -2289,7 +2289,7 @@ asm_1:
 	    return yyerror ("Register mismatch");
 	}
 
-	| a_assign ROT REG_A BY expr 
+	| a_assign ROT REG_A BY expr
 	{
 	  if (IS_IMM ($5, 6))
 	    {
@@ -2300,7 +2300,7 @@ asm_1:
 	    return yyerror ("Register mismatch");
 	}
 
-	| REG ASSIGN ROT REG BY expr 
+	| REG ASSIGN ROT REG BY expr
 	{
 	  if (IS_DREG ($1) && IS_DREG ($4) && IS_IMM ($6, 6))
 	    {
@@ -2342,9 +2342,9 @@ asm_1:
 	  else
 	    return yyerror ("Register mismatch");
 	}
-	
+
 	/* The ASR bit is just inverted here. */
-	| HALF_REG ASSIGN VIT_MAX LPAREN REG RPAREN asr_asl 
+	| HALF_REG ASSIGN VIT_MAX LPAREN REG RPAREN asr_asl
 	{
 	  if (IS_DREG_L ($1) && IS_DREG ($5))
 	    {
@@ -2355,7 +2355,7 @@ asm_1:
 	    return yyerror ("Register mismatch");
 	}
 
-	| REG ASSIGN VIT_MAX LPAREN REG COMMA REG RPAREN asr_asl 
+	| REG ASSIGN VIT_MAX LPAREN REG COMMA REG RPAREN asr_asl
 	{
 	  if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
 	    {
@@ -2971,7 +2971,7 @@ asm_1:
 
 	  if ($4.r0)
 	    tmp = unary (Expr_Op_Type_NEG, tmp);
-	    
+
 	  if (in_range_p (tmp, -32768, 32767, 0))
 	    {
 	      notethat ("LDST: B [ pregs + imm16 ] = dregs\n");
@@ -2991,7 +2991,7 @@ asm_1:
 	    return yyerror ("Dreg expected for source operand");
 	  if (!IS_PREG ($3))
 	    return yyerror ("Preg expected in address");
-	  
+
 	  if ($4.r0)
 	    tmp = unary (Expr_Op_Type_NEG, tmp);
 
@@ -3112,7 +3112,7 @@ asm_1:
 	    }
 	  else
 	    return yyerror ("Displacement out of range");
-	}	
+	}
 
 	| HALF_REG ASSIGN W LBRACK REG post_op RBRACK
 	{
@@ -3216,7 +3216,7 @@ asm_1:
 	  else
 	    return yyerror ("Preg ++ Preg or Ireg ++ Mreg expected in address");
 	}
-			
+
 	| W LBRACK REG _PLUS_PLUS REG RBRACK ASSIGN HALF_REG
 	{
 	  if (!IS_DREG ($8))
@@ -3266,7 +3266,7 @@ asm_1:
 		    $8.r0 ? 'X' : 'Z');
 	  $$ = LDST (&$5, &$1, $6.x0, 2, $8.r0, 0);
 	}
-			
+
 	| REG ASSIGN LBRACK REG _PLUS_PLUS REG RBRACK
 	{
 	  if (!IS_DREG ($1))
@@ -3326,7 +3326,7 @@ asm_1:
 	    {
 	      notethat ("LDSTidxI: dpregs = [ pregs + imm18m4 ]\n");
 	      $$ = LDSTIDXI (&$4, &$1, 0, 0, ispreg ? 1 : 0, tmp);
-	      
+
 	    }
 	  else
 	    return yyerror ("Displacement out of range");
@@ -3460,7 +3460,7 @@ asm_1:
 	  else
 	    return yyerror ("Bad constant for LINK");
 	}
-		
+
 	| UNLINK
 	{
 		notethat ("linkage: UNLINK\n");
@@ -3479,7 +3479,7 @@ asm_1:
 	    }
 	  else
 	    return yyerror ("Bad register or values for LSETUP");
-	  
+
 	}
 	| LSETUP LPAREN expr COMMA expr RPAREN REG ASSIGN REG
 	{
@@ -3496,7 +3496,7 @@ asm_1:
 	| LSETUP LPAREN expr COMMA expr RPAREN REG ASSIGN REG GREATER_GREATER expr
 	{
 	  if (IS_PCREL4 ($3) && IS_LPPCREL10 ($5)
-	      && IS_PREG ($9) && IS_CREG ($7) 
+	      && IS_PREG ($9) && IS_CREG ($7)
 	      && EXPR_VALUE ($11) == 1)
 	    {
 	      notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters = pregs >> 1\n");
@@ -3581,7 +3581,7 @@ asm_1:
 	  notethat ("pseudoDEBUG: DBGCMPLX (dregs )\n");
 	  $$ = bfin_gen_pseudodbg (3, 6, $3.regno & CODE_MASK);
 	}
-	
+
 	| DBGHALT
 	{
 	  notethat ("psedoDEBUG: DBGHALT\n");
@@ -3685,7 +3685,7 @@ sco:
 	$$.x0 = 1;
 	}
 	| SCO
-	{	
+	{
 	$$.s0 = 1;
 	$$.x0 = 1;
 	}
@@ -3975,7 +3975,7 @@ min_max:
 	$$.r0 = 0;
 	}
 	;
- 
+
 op_bar_op:
 	_PLUS_BAR_PLUS
 	{
@@ -4096,8 +4096,8 @@ b3_op:
 post_op:
 	{
 	$$.x0 = 2;
-	} 
-	| _PLUS_PLUS 
+	}
+	| _PLUS_PLUS
 	{
 	$$.x0 = 0;
 	}
@@ -4374,7 +4374,7 @@ expr_1: expr_1 STAR expr_1
 	}
 	| expr_1 LESS_LESS expr_1
 	{
-	$$ = binary (Expr_Op_Type_Lshift, $1, $3);	
+	$$ = binary (Expr_Op_Type_Lshift, $1, $3);
 	}
 	| expr_1 GREATER_GREATER expr_1
 	{
@@ -4392,7 +4392,7 @@ expr_1: expr_1 STAR expr_1
 	{
 	$$ = binary (Expr_Op_Type_BOR, $1, $3);
 	}
-	| eterm	
+	| eterm
 	{
 	$$ = $1;
 	}
@@ -4416,12 +4416,12 @@ value_match (Expr_Node *exp, int sz, int sign, int mul, int issigned)
   int umax = (1 << sz) - 1;
   int min = -1 << (sz - 1);
   int max = (1 << (sz - 1)) - 1;
-	
+
   int v = (EXPR_VALUE (exp)) & 0xffffffff;
 
   if ((v % mul) != 0)
     {
-      error ("%s:%d: Value Error -- Must align to %d\n", __FILE__, __LINE__, mul); 
+      error ("%s:%d: Value Error -- Must align to %d\n", __FILE__, __LINE__, mul);
       return 0;
     }
 
@@ -4439,7 +4439,7 @@ value_match (Expr_Node *exp, int sz, int sign, int mul, int issigned)
 #endif
       return 0;
     }
-  if (v <= umax && v >= 0) 
+  if (v <= umax && v >= 0)
     return 1;
 #ifdef DEBUG
   fprintf(stderr, "unsigned value %lx out of range\n", v * mul);
@@ -4458,43 +4458,43 @@ binary (Expr_Op_Type op, Expr_Node *x, Expr_Node *y)
     {
       switch (op)
 	{
-        case Expr_Op_Type_Add: 
+        case Expr_Op_Type_Add:
 	  x->value.i_value += y->value.i_value;
 	  break;
-        case Expr_Op_Type_Sub: 
+        case Expr_Op_Type_Sub:
 	  x->value.i_value -= y->value.i_value;
 	  break;
-        case Expr_Op_Type_Mult: 
+        case Expr_Op_Type_Mult:
 	  x->value.i_value *= y->value.i_value;
 	  break;
-        case Expr_Op_Type_Div: 
+        case Expr_Op_Type_Div:
 	  if (y->value.i_value == 0)
 	    error ("Illegal Expression:  Division by zero.");
 	  else
 	    x->value.i_value /= y->value.i_value;
 	  break;
-        case Expr_Op_Type_Mod: 
+        case Expr_Op_Type_Mod:
 	  x->value.i_value %= y->value.i_value;
 	  break;
-        case Expr_Op_Type_Lshift: 
+        case Expr_Op_Type_Lshift:
 	  x->value.i_value <<= y->value.i_value;
 	  break;
-        case Expr_Op_Type_Rshift: 
+        case Expr_Op_Type_Rshift:
 	  x->value.i_value >>= y->value.i_value;
 	  break;
-        case Expr_Op_Type_BAND: 
+        case Expr_Op_Type_BAND:
 	  x->value.i_value &= y->value.i_value;
 	  break;
-        case Expr_Op_Type_BOR: 
+        case Expr_Op_Type_BOR:
 	  x->value.i_value |= y->value.i_value;
 	  break;
-        case Expr_Op_Type_BXOR: 
+        case Expr_Op_Type_BXOR:
 	  x->value.i_value ^= y->value.i_value;
 	  break;
-        case Expr_Op_Type_LAND: 
+        case Expr_Op_Type_LAND:
 	  x->value.i_value = x->value.i_value && y->value.i_value;
 	  break;
-        case Expr_Op_Type_LOR: 
+        case Expr_Op_Type_LOR:
 	  x->value.i_value = x->value.i_value || y->value.i_value;
 	  break;
 
@@ -4532,13 +4532,13 @@ binary (Expr_Op_Type op, Expr_Node *x, Expr_Node *y)
 }
 
 static Expr_Node *
-unary (Expr_Op_Type op, Expr_Node *x) 
+unary (Expr_Op_Type op, Expr_Node *x)
 {
   if (x->type == Expr_Node_Constant)
     {
       switch (op)
 	{
-	case Expr_Op_Type_NEG: 
+	case Expr_Op_Type_NEG:
 	  x->value.i_value = -x->value.i_value;
 	  break;
 	case Expr_Op_Type_COMP: