RISC-V: Add support for Zvfbfmin extension

This implements the Zvfbfmin extension, as of version 1.0.
View detailed information in:
<https://github.com/riscv/riscv-isa-manual/blob/main/src/bfloat16.adoc#zvfbfmin---vector-bf16-converts>

Depending on different usage scenarios, the Zvfbfmin extension may
depend on 'V' or 'Zve32f'. This patch only implements dependencies
in scenario of Embedded Processor. In scenario of Application
Processor, it is necessary to explicitly indicate the dependent
'V' extension.

For relevant information in gcc, please refer to:
<https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=1ddf65c5fc6ba7cf5826e1c02c569c923a541c09>

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_multi_subset_supports): Handle Zvfbfmin.
	(riscv_multi_subset_supports_ext): Ditto.

gas/ChangeLog:

	* NEWS: Updated.
	* testsuite/gas/riscv/march-help.l: Ditto.
	* testsuite/gas/riscv/zvfbfmin.d: New test.
	* testsuite/gas/riscv/zvfbfmin.s: New test.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_VFNCVTBF16_F_F_W): Define.
	(MASK_VFNCVTBF16_F_F_W): Ditto.
	(MATCH_VFWCVTBF16_F_F_V): Ditto.
	(MASK_VFWCVTBF16_F_F_V): Ditto.
	(DECLARE_INSN): New declarations for Zvfbfmin.
	* opcode/riscv.h (enum riscv_insn_class): Add
	INSN_CLASS_ZVFBFMIN

opcodes/ChangeLog:

	* riscv-opc.c: Add Zvfbfmin instructions.

1 files changed, 2 insertions, 0 deletions

diff --git a/gas/NEWS b/gas/NEWS
index cdf3094..a668a52 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -23,6 +23,8 @@
 
 * Add support for RISC-V Zfbfmin extension with version 1.0.
 
+* Add support for RISC-V Zvfbfmin extension with version 1.0.
+
 * The base register operand in D(X,B) and D(L,B) may be explicitly omitted
   in assembly on s390. It can now be coded as D(X,) or D(L,) instead of D(X,0)
   D(X,%r0), D(L,0), and D(L,%r0).