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authorsaurabh.jha@arm.com <saurabh.jha@arm.com>2024-06-21 16:30:59 +0100
committerRichard Earnshaw <rearnsha@arm.com>2024-06-24 15:00:40 +0100
commitadea87e275802fb7afe7acefae1477f692c48969 (patch)
tree8b7ef7d13df4366cfb917425a09bb3e95cd14ce9 /gas/NEWS
parentc702f1ad8a6a51b9c74445c77e1f6e822ba9293b (diff)
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gas, aarch64: Add SME2 lutv2 extension
Introduces instructions for the SME2 lutv2 extension for AArch64. They are documented in the following document: * ARM DDI0602 For both luti4 instructions, we introduced an operand called SME_Znx2_BIT_INDEX. We use the existing function parse_vector_reg_list for parsing but modified that function so that it can accept operands without qualifiers and rejects instructions that have operands with qualifiers but are not supposed to have operands with qualifiers. For disassembly, we modified print_register_list so that it could accept register lists without qualifiers. For one luti4 instruction, we introduced a SME_Zdnx4_STRIDED. It is similar to SME_Ztx4_STRIDED and we could use existing code for parsing, encoding, and disassembly. For movt instruction, we introduced an operand called SME_ZT0_INDEX2_12. This is a ZT0 register with a bit index encoded in [13:12]. It is similar to SME_ZT0_INDEX. We also introduced an iclass named sme_size_12_b so that we can encode size bits [13:12] correctly when only 'b' is allowed as qualifier.
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* Add support for the AArch64 Lookup Table Extension (LUT).
+* Add support for the AArch64 Lookup Table Extension v2 (LUTv2).
+
Changes in 2.42:
* Add support for AMD znver5 processor.