diff options
| author | Nelson Chu <nelson.chu@sifive.com> | 2023-11-24 15:46:56 +0800 |
|---|---|---|
| committer | Nelson Chu <nelson@rivosinc.com> | 2023-12-01 09:29:07 +0800 |
| commit | 248bf6de04032c666cbbd8d3278efa60b6059660 (patch) | |
| tree | 2d4ddc632b91b3f3058b55d6d16868afca30472a /gas/NEWS | |
| parent | ea1bd007428cb20df9a36a049d3a0ccd9ae74894 (diff) | |
| download | gdb-248bf6de04032c666cbbd8d3278efa60b6059660.zip gdb-248bf6de04032c666cbbd8d3278efa60b6059660.tar.gz gdb-248bf6de04032c666cbbd8d3278efa60b6059660.tar.bz2 | |
RISC-V: Add SiFive custom vector coprocessor interface instructions v1.0
SiFive has define as set of flexible instruction for extending vector
coprocessor, it able to encoding opcode like .insn but with predefined
format.
List of instructions:
sf.vc.x
sf.vc.i
sf.vc.vv
sf.vc.xv
sf.vc.iv
sf.vc.fv
sf.vc.vvv
sf.vc.xvv
sf.vc.ivv
sf.vc.fvv
sf.vc.vvw
sf.vc.xvw
sf.vc.ivw
sf.vc.fvw
sf.vc.v.x
sf.vc.v.i
sf.vc.v.vv
sf.vc.v.xv
sf.vc.v.iv
sf.vc.v.fv
sf.vc.v.vvv
sf.vc.v.xvv
sf.vc.v.ivv
sf.vc.v.fvv
sf.vc.v.vvw
sf.vc.v.xvw
sf.vc.v.ivw
sf.vc.v.fvw
Spec of Xsfvcp
https://www.sifive.com/document-file/sifive-vector-coprocessor-interface-vcix-software
Co-authored-by: Hau Hsu <hau.hsu@sifive.com>
Co-authored-by: Kito Cheng <kito.cheng@sifive.com>
Diffstat (limited to 'gas/NEWS')
| -rw-r--r-- | gas/NEWS | 2 |
1 files changed, 2 insertions, 0 deletions
@@ -37,6 +37,8 @@ * Add support for various T-Head extensions (XTheadVector, XTheadZvlsseg and XTheadZvamo) from version 2.3.0 of the T-Head ISA manual. +* Add support for RISC-V SiFive VCIX extension (XSfVcp) with version 1.0. + * The BPF assembler now uses semi-colon (;) to separate statements, and therefore they cannot longer be used to begin line comments. This matches the behavior of the clang/LLVM BPF assembler. |