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| author | Sudakshina Das <sudi.das@arm.com> | 2019-05-21 18:15:13 +0100 |
|---|---|---|
| committer | Sudakshina Das <sudi.das@arm.com> | 2019-05-21 18:15:13 +0100 |
| commit | e39c1607a2df3a97bf7b70bef6de5b7a2db55eea (patch) | |
| tree | 4fbd7358df529b544ef84d586e471fd9a574eaa5 /gas/ChangeLog | |
| parent | 23d00a419fe67801afc02a87f7ab9c5374b0238e (diff) | |
| download | gdb-e39c1607a2df3a97bf7b70bef6de5b7a2db55eea.zip gdb-e39c1607a2df3a97bf7b70bef6de5b7a2db55eea.tar.gz gdb-e39c1607a2df3a97bf7b70bef6de5b7a2db55eea.tar.bz2 | |
[binutils, Arm] Add support for conditional instructions in Armv8.1-M Mainline
This patch adds the following instructions which are part of the
Armv8.1-M Mainline:
CINC
CINV
CNEG
CSINC
CSINV
CSNEG
CSET
CSETM
CSEL
gas/ChangeLog:
2019-05-21 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (TOGGLE_BIT): New.
(T16_32_TAB): New entries for cinc, cinv, cneg, csinc,
csinv, csneg, cset, csetm and csel.
(operand_parse_code): New OP_RR_ZR.
(parse_operand): Handle case for OP_RR_ZR.
(do_t_cond): New.
(insns): New instructions for cinc, cinv, cneg, csinc,
csinv, csneg, cset, csetm, csel.
* testsuite/gas/arm/armv8_1-m-cond-bad.d: New test.
* testsuite/gas/arm/armv8_1-m-cond-bad.l: New test.
* testsuite/gas/arm/armv8_1-m-cond-bad.s: New test.
* testsuite/gas/arm/armv8_1-m-cond.d: New test.
* testsuite/gas/arm/armv8_1-m-cond.s: New test.
opcodes/ChangeLog:
2019-05-21 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (enum mve_instructions): New enum
for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
and cneg.
(mve_opcodes): New instructions as above.
(is_mve_encoding_conflict): Add cases for csinc, csinv,
csneg and csel.
(print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
Diffstat (limited to 'gas/ChangeLog')
| -rw-r--r-- | gas/ChangeLog | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 34fee55..fc1fb65 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,5 +1,21 @@ 2019-05-21 Sudakshina Das <sudi.das@arm.com> + * config/tc-arm.c (TOGGLE_BIT): New. + (T16_32_TAB): New entries for cinc, cinv, cneg, csinc, + csinv, csneg, cset, csetm and csel. + (operand_parse_code): New OP_RR_ZR. + (parse_operand): Handle case for OP_RR_ZR. + (do_t_cond): New. + (insns): New instructions for cinc, cinv, cneg, csinc, + csinv, csneg, cset, csetm, csel. + * testsuite/gas/arm/armv8_1-m-cond-bad.d: New test. + * testsuite/gas/arm/armv8_1-m-cond-bad.l: New test. + * testsuite/gas/arm/armv8_1-m-cond-bad.s: New test. + * testsuite/gas/arm/armv8_1-m-cond.d: New test. + * testsuite/gas/arm/armv8_1-m-cond.s: New test. + +2019-05-21 Sudakshina Das <sudi.das@arm.com> + * config/tc-arm.c (operand_parse_code): New entries for OP_RRnpcsp_I32 (register or integer operands). (do_mve_scalar_shift): New. |