diff options
| author | H.J. Lu <hjl.tools@gmail.com> | 2020-01-27 04:38:10 -0800 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2020-01-27 04:38:29 -0800 |
| commit | bc31405ebb2c4297ae815ab59f59165014347528 (patch) | |
| tree | 4298be1f20f511497e961d2e672f38b0d2e75bf6 /gas/ChangeLog | |
| parent | e3696f67abfc46dcac6c9bbe47f8e25e34b17be5 (diff) | |
| download | gdb-bc31405ebb2c4297ae815ab59f59165014347528.zip gdb-bc31405ebb2c4297ae815ab59f59165014347528.tar.gz gdb-bc31405ebb2c4297ae815ab59f59165014347528.tar.bz2 | |
x86-64: Properly encode and decode movsxd
movsxd is a 64-bit only instruction. It supports both 16-bit and 32-bit
destination registers. Its AT&T mnemonic is movslq which only supports
64-bit destination register. There is also a discrepancy between AMD64
and Intel64 on movsxd with 16-bit destination register. AMD64 supports
32-bit source operand and Intel64 supports 16-bit source operand.
This patch updates movsxd encoding and decoding to alow 16-bit and 32-bit
destination registers. It also handles movsxd with 16-bit destination
register for AMD64 and Intel 64.
gas/
PR binutils/25445
* config/tc-i386.c (check_long_reg): Also convert to QWORD for
movsxd.
* doc/c-i386.texi: Add a node for AMD64 vs. Intel64 ISA
differences. Document movslq and movsxd.
* testsuite/gas/i386/i386.exp: Run PR binutils/25445 tests.
* testsuite/gas/i386/x86-64-movsxd-intel.d: New file.
* testsuite/gas/i386/x86-64-movsxd-intel64-intel.d: Likewise.
* testsuite/gas/i386/x86-64-movsxd-intel64-inval.l: Likewise.
* testsuite/gas/i386/x86-64-movsxd-intel64-inval.s: Likewise.
* testsuite/gas/i386/x86-64-movsxd-intel64.d: Likewise.
* testsuite/gas/i386/x86-64-movsxd-intel64.s: Likewise.
* testsuite/gas/i386/x86-64-movsxd-inval.l: Likewise.
* testsuite/gas/i386/x86-64-movsxd-inval.s: Likewise.
* testsuite/gas/i386/x86-64-movsxd.d: Likewise.
* testsuite/gas/i386/x86-64-movsxd.s: Likewise.
opcodes/
PR binutils/25445
* i386-dis.c (MOVSXD_Fixup): New function.
(movsxd_mode): New enum.
(x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
(intel_operand_size): Handle movsxd_mode.
(OP_E_register): Likewise.
(OP_G): Likewise.
* i386-opc.tbl: Remove Rex64 and allow 32-bit destination
register on movsxd. Add movsxd with 16-bit destination register
for AMD64 and Intel64 ISAs.
* i386-tbl.h: Regenerated.
Diffstat (limited to 'gas/ChangeLog')
| -rw-r--r-- | gas/ChangeLog | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 6c182f5..9109784 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,22 @@ +2020-01-27 H.J. Lu <hongjiu.lu@intel.com> + + PR binutils/25445 + * config/tc-i386.c (check_long_reg): Also convert to QWORD for + movsxd. + * doc/c-i386.texi: Add a node for AMD64 vs. Intel64 ISA + differences. Document movslq and movsxd. + * testsuite/gas/i386/i386.exp: Run PR binutils/25445 tests. + * testsuite/gas/i386/x86-64-movsxd-intel.d: New file. + * testsuite/gas/i386/x86-64-movsxd-intel64-intel.d: Likewise. + * testsuite/gas/i386/x86-64-movsxd-intel64-inval.l: Likewise. + * testsuite/gas/i386/x86-64-movsxd-intel64-inval.s: Likewise. + * testsuite/gas/i386/x86-64-movsxd-intel64.d: Likewise. + * testsuite/gas/i386/x86-64-movsxd-intel64.s: Likewise. + * testsuite/gas/i386/x86-64-movsxd-inval.l: Likewise. + * testsuite/gas/i386/x86-64-movsxd-inval.s: Likewise. + * testsuite/gas/i386/x86-64-movsxd.d: Likewise. + * testsuite/gas/i386/x86-64-movsxd.s: Likewise. + 2020-01-27 Alan Modra <amodra@gmail.com> * testsuite/gas/all/gas.exp: Replace case statements with switch |