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| author | Jan Beulich <jbeulich@suse.com> | 2020-07-08 11:02:40 +0200 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2020-07-08 11:02:40 +0200 |
| commit | 93abb1468ea24f721b2ed025118f4b4412900b37 (patch) | |
| tree | 1ea662b1c30a00dd9fa3affe57e37ae3291f7082 /cpu | |
| parent | b13b1bc05435d2b8b2f1a0f48eba127a7c99fbb4 (diff) | |
| download | gdb-93abb1468ea24f721b2ed025118f4b4412900b37.zip gdb-93abb1468ea24f721b2ed025118f4b4412900b37.tar.gz gdb-93abb1468ea24f721b2ed025118f4b4412900b37.tar.bz2 | |
x86: re-work operand handling for 5-operand XOP insns
There's no need for custom operand handling here, except for the VEX.W
controlled operand swapping and the printing of the remaining 4-bit
immediate. VEX.W can be handled just like 4-operand insns.
Also take the opportunity and drop the stray indirection through
vex_w_table[].
Diffstat (limited to 'cpu')
0 files changed, 0 insertions, 0 deletions