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| author | Andrew Waterman <andrew@sifive.com> | 2016-12-18 22:53:52 -0800 |
|---|---|---|
| committer | Alan Modra <amodra@gmail.com> | 2016-12-20 12:26:34 +1030 |
| commit | 755c5297bdbca564e97040ce7f036ed02dc7fa4a (patch) | |
| tree | 1017211f4410afc70a0af19b6d4805cd9051b1e3 /cpu/m32r.cpu | |
| parent | d115ab8eee9bb3e13aae86698a4fd91e0ed284e9 (diff) | |
| download | gdb-755c5297bdbca564e97040ce7f036ed02dc7fa4a.zip gdb-755c5297bdbca564e97040ce7f036ed02dc7fa4a.tar.gz gdb-755c5297bdbca564e97040ce7f036ed02dc7fa4a.tar.bz2 | |
Add canonical JALR for RISC-V
jalr rd,offset(rs1)
rather than
jalr rd,rs1,offset
This matches the format of other instructions.
* riscv-opc.c (riscv_opcodes): Change jr and jalr to "o(s)"
format.
Diffstat (limited to 'cpu/m32r.cpu')
0 files changed, 0 insertions, 0 deletions