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authorMike Frysinger <vapier@gentoo.org>2015-05-21 23:16:45 +0800
committerMike Frysinger <vapier@gentoo.org>2021-02-04 19:02:19 -0500
commitb9249c461c72b35dd9b6f274406c336f6a68ae98 (patch)
tree2f2314445c8c95e8dc1c3c8de6d824e9042b15fe /compile
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sim: riscv: new port
This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
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