Arm: Fix Arm disassembler mapping symbol search.

Similar to the AArch64 patches the Arm disassembler has the same issues with
out of order sections but also a few short comings.

For one thing there are multiple code blocks to determine mapping symbols, and
they all work slightly different, and neither fully correct.  The first thing
this patch does is centralise the mapping symbols search into one function
mapping_symbol_for_insn.  This function is then updated to perform a search in
a similar way as AArch64.

Their used to be a value has_mapping_symbols which was used to determine the
default disassembly for objects that have no mapping symbols.  The problem with
the approach was that it was determining this value in the same loop that needed
it, which is why this field could take on the states -1, 0, 1 where -1 means
"don't know".  However this means that until you actually find a mapping symbol
or reach the end of the disassembly glob, you don't know if you did the right
action or not, and if you didn't you can't correct it anymore.

This is why the two jump-reloc-veneers-* testcases end up disassembling some
insn as data when they shouldn't.

Out of order here refers to an object file where sections are not listed in a
monotonic increasing VMA order.

The ELF ABI for Arm [1] specifies the following for mapping symbols:

  1) A text section must always have a corresponding mapping symbol at it's
     start.
  2) Data sections do not require any mapping symbols.
  3) The range of a mapping symbol extends from the address it starts on up to
     the next mapping symbol (exclusive) or section end (inclusive).

However there is no defined order between a symbol and it's corresponding
mapping symbol in the symbol table.  This means that while in general we look
up for a corresponding mapping symbol, we have to make at least one check of
the symbol below the address being disassembled.

When disassembling different PCs within the same section, the search for mapping
symbol can be cached somewhat.  We know that the mapping symbol corresponding to
the current PC is either the previous one used, or one at the same address as
the current PC.

However this optimization and mapping symbol search must stop as soon as we
reach the end or start of the section.  Furthermore if we're only disassembling
a part of a section, the search is a allowed to search further than the current
chunk, but is not allowed to search past it (The mapping symbol if there, must
be at the same address, so in practice we usually stop at PC+4).

lastly, since only data sections don't require a mapping symbol the default
mapping type should be DATA and not INSN as previously defined, however if the
binary has had all its symbols stripped than this isn't very useful.  To fix
this we determine the default based on the section flags.  This will allow the
disassembler to be more useful on stripped binaries.  If there is no section
than we assume you to be disassembling INSN.

[1] https://developer.arm.com/docs/ihi0044/latest/elf-for-the-arm-architecture-abi-2018q4-documentation#aaelf32-table4-7

binutils/ChangeLog:

	* testsuite/binutils-all/arm/in-order-all.d: New test.
	* testsuite/binutils-all/arm/in-order.d: New test.
	* testsuite/binutils-all/arm/objdump.exp: Support .d tests.
	* testsuite/binutils-all/arm/out-of-order-all.d: New test.
	* testsuite/binutils-all/arm/out-of-order.T: New test.
	* testsuite/binutils-all/arm/out-of-order.d: New test.
	* testsuite/binutils-all/arm/out-of-order.s: New test.

ld/ChangeLog:

	* testsuite/ld-arm/jump-reloc-veneers-cond-long.d: Update disassembly.
	* testsuite/ld-arm/jump-reloc-veneers-long.d: Update disassembly.

opcodes/ChangeLog:

	* arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
	(mapping_symbol_for_insn): Implement new algorithm.
	(print_insn): Remove duplicate code.

7 files changed, 212 insertions, 0 deletions

diff --git a/binutils/testsuite/binutils-all/arm/in-order-all.d b/binutils/testsuite/binutils-all/arm/in-order-all.d
new file mode 100644
index 0000000..3a098dd
--- /dev/null
+++ b/binutils/testsuite/binutils-all/arm/in-order-all.d
@@ -0,0 +1,50 @@
+#PROG: objcopy
+#source: out-of-order.s
+#ld: -e v1 -Ttext-segment=0x400000
+#objdump: -D
+#name: Check if disassembler can handle all sections in default order
+
+.*: +file format .*arm.*
+
+Disassembly of section \.func1:
+
+00400000 <v1>:
+  400000:	e0800001 	add	r0, r0, r1
+  400004:	00000000 	andeq	r0, r0, r0
+
+Disassembly of section \.func2:
+
+00400008 <\.func2>:
+  400008:	e0800001 	add	r0, r0, r1
+
+Disassembly of section \.func3:
+
+0040000c <\.func3>:
+  40000c:	e0800001 	add	r0, r0, r1
+  400010:	e0800001 	add	r0, r0, r1
+  400014:	e0800001 	add	r0, r0, r1
+  400018:	e0800001 	add	r0, r0, r1
+  40001c:	e0800001 	add	r0, r0, r1
+  400020:	00000000 	andeq	r0, r0, r0
+
+Disassembly of section \.rodata:
+
+00400024 <\.rodata>:
+  400024:	00000004 	andeq	r0, r0, r4
+
+Disassembly of section \.global:
+
+00410028 <__data_start>:
+  410028:	00000001 	andeq	r0, r0, r1
+  41002c:	00000001 	andeq	r0, r0, r1
+  410030:	00000001 	andeq	r0, r0, r1
+
+Disassembly of section \.ARM\.attributes:
+
+00000000 <\.ARM\.attributes>:
+   0:	00001141 	andeq	r1, r0, r1, asr #2
+   4:	61656100 	cmnvs	r5, r0, lsl #2
+   8:	01006962 	tsteq	r0, r2, ror #18
+   c:	00000007 	andeq	r0, r0, r7
+  10:	Address 0x0000000000000010 is out of bounds.
+
diff --git a/binutils/testsuite/binutils-all/arm/in-order.d b/binutils/testsuite/binutils-all/arm/in-order.d
new file mode 100644
index 0000000..a0b63c2
--- /dev/null
+++ b/binutils/testsuite/binutils-all/arm/in-order.d
@@ -0,0 +1,28 @@
+#PROG: objcopy
+#source: out-of-order.s
+#ld: -e v1 -Ttext-segment=0x400000
+#objdump: -d
+#name: Check if disassembler can handle sections in default order
+
+.*: +file format .*arm.*
+
+Disassembly of section \.func1:
+
+00400000 <v1>:
+  400000:	e0800001 	add	r0, r0, r1
+  400004:	00000000 	\.word	0x00000000
+
+Disassembly of section \.func2:
+
+00400008 <\.func2>:
+  400008:	e0800001 	add	r0, r0, r1
+
+Disassembly of section \.func3:
+
+0040000c <\.func3>:
+  40000c:	e0800001 	add	r0, r0, r1
+  400010:	e0800001 	add	r0, r0, r1
+  400014:	e0800001 	add	r0, r0, r1
+  400018:	e0800001 	add	r0, r0, r1
+  40001c:	e0800001 	add	r0, r0, r1
+  400020:	00000000 	\.word	0x00000000
diff --git a/binutils/testsuite/binutils-all/arm/objdump.exp b/binutils/testsuite/binutils-all/arm/objdump.exp
index 5013b18..33e3fd1 100644
--- a/binutils/testsuite/binutils-all/arm/objdump.exp
+++ b/binutils/testsuite/binutils-all/arm/objdump.exp
@@ -111,3 +111,17 @@ if {![binutils_assemble $srcdir/$subdir/rvct_symbol.s tmpdir/rvct_symbol.o]} the
 	fail "skip rvct symbol"
     }
 }
+
+###########################
+# Set up generic test framework
+###########################
+
+set tempfile tmpdir/armtemp.o
+set copyfile tmpdir/armcopy
+
+set test_list [lsort [glob -nocomplain $srcdir/$subdir/*.d]]
+foreach t $test_list {
+    # We need to strip the ".d", but can leave the dirname.
+    verbose [file rootname $t]
+    run_dump_test [file rootname $t]
+}
diff --git a/binutils/testsuite/binutils-all/arm/out-of-order-all.d b/binutils/testsuite/binutils-all/arm/out-of-order-all.d
new file mode 100644
index 0000000..58c4057
--- /dev/null
+++ b/binutils/testsuite/binutils-all/arm/out-of-order-all.d
@@ -0,0 +1,50 @@
+#PROG: objcopy
+#source: out-of-order.s
+#ld: -T out-of-order.T
+#objdump: -D
+#name: Check if disassembler can handle all sections in different order than header
+
+.*: +file format .*arm.*
+
+Disassembly of section \.global:
+
+ffe00000 <\.global>:
+ffe00000:	00000001 	andeq	r0, r0, r1
+ffe00004:	00000001 	andeq	r0, r0, r1
+ffe00008:	00000001 	andeq	r0, r0, r1
+
+Disassembly of section \.func2:
+
+04018280 <\.func2>:
+ 4018280:	e0800001 	add	r0, r0, r1
+
+Disassembly of section \.func1:
+
+04005000 <v1>:
+ 4005000:	e0800001 	add	r0, r0, r1
+ 4005004:	00000000 	andeq	r0, r0, r0
+
+Disassembly of section \.func3:
+
+04015000 <\.func3>:
+ 4015000:	e0800001 	add	r0, r0, r1
+ 4015004:	e0800001 	add	r0, r0, r1
+ 4015008:	e0800001 	add	r0, r0, r1
+ 401500c:	e0800001 	add	r0, r0, r1
+ 4015010:	e0800001 	add	r0, r0, r1
+ 4015014:	00000000 	andeq	r0, r0, r0
+
+Disassembly of section \.rodata:
+
+04015018 <\.rodata>:
+ 4015018:	00000004 	andeq	r0, r0, r4
+
+Disassembly of section \.ARM\.attributes:
+
+00000000 <\.ARM\.attributes>:
+   0:	00001141 	andeq	r1, r0, r1, asr #2
+   4:	61656100 	cmnvs	r5, r0, lsl #2
+   8:	01006962 	tsteq	r0, r2, ror #18
+   c:	00000007 	andeq	r0, r0, r7
+  10:	Address 0x0000000000000010 is out of bounds.
+
diff --git a/binutils/testsuite/binutils-all/arm/out-of-order.T b/binutils/testsuite/binutils-all/arm/out-of-order.T
new file mode 100644
index 0000000..489ae80
--- /dev/null
+++ b/binutils/testsuite/binutils-all/arm/out-of-order.T
@@ -0,0 +1,14 @@
+ENTRY(v1)
+SECTIONS
+{
+  . = 0xffe00000;
+  .global : { *(.global) }
+  . = 0x4018280;
+  .func2 : { *(.func2) }
+  . = 0x4005000;
+  .func1 : { *(.func1) }
+  . = 0x4015000;
+  .func3 : { *(.func3) }
+  .data : { *(.data) }
+  .rodata : { *(.rodata) }
+}
\ No newline at end of file
diff --git a/binutils/testsuite/binutils-all/arm/out-of-order.d b/binutils/testsuite/binutils-all/arm/out-of-order.d
new file mode 100644
index 0000000..9351af7
--- /dev/null
+++ b/binutils/testsuite/binutils-all/arm/out-of-order.d
@@ -0,0 +1,27 @@
+#PROG: objcopy
+#ld: -T out-of-order.T
+#objdump: -d
+#name: Check if disassembler can handle sections in different order than header
+
+.*: +file format .*arm.*
+
+Disassembly of section \.func2:
+
+04018280 <\.func2>:
+ 4018280:	e0800001 	add	r0, r0, r1
+
+Disassembly of section \.func1:
+
+04005000 <v1>:
+ 4005000:	e0800001 	add	r0, r0, r1
+ 4005004:	00000000 	\.word	0x00000000
+
+Disassembly of section \.func3:
+
+04015000 <\.func3>:
+ 4015000:	e0800001 	add	r0, r0, r1
+ 4015004:	e0800001 	add	r0, r0, r1
+ 4015008:	e0800001 	add	r0, r0, r1
+ 401500c:	e0800001 	add	r0, r0, r1
+ 4015010:	e0800001 	add	r0, r0, r1
+ 4015014:	00000000 	\.word	0x00000000
diff --git a/binutils/testsuite/binutils-all/arm/out-of-order.s b/binutils/testsuite/binutils-all/arm/out-of-order.s
new file mode 100644
index 0000000..4e43ddf
--- /dev/null
+++ b/binutils/testsuite/binutils-all/arm/out-of-order.s
@@ -0,0 +1,29 @@
+	.text
+	.arm
+	.global v1
+	.section .func1,"ax",%progbits
+	.type v1 %function
+	.size v1, 4
+v1:
+	add r0, r0, r1
+	.word 0
+
+	.section .func2,"ax",%progbits
+	add r0, r0, r1
+
+	.section .func3,"ax",%progbits
+	add r0, r0, r1
+	add r0, r0, r1
+	add r0, r0, r1
+	add r0, r0, r1
+	add r0, r0, r1
+	.word 0
+
+	.data
+	.section .global,"aw",%progbits
+	.word 1
+	.word 1
+	.word 1
+
+	.section .rodata
+	.word 4