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| author | Tsukasa OI <research_trasio@irq.a4lg.com> | 2023-08-03 05:35:53 +0000 |
|---|---|---|
| committer | Tsukasa OI <research_trasio@irq.a4lg.com> | 2023-08-03 05:58:21 +0000 |
| commit | e57ed3695a65ecbc76c195ad0535657150b7d5d9 (patch) | |
| tree | 26bb86e48e1be037a018bb2fc90e206476658dd5 /bfd | |
| parent | 92f46037a0f672d1480f754f76a9bfa0334d099c (diff) | |
| download | gdb-e57ed3695a65ecbc76c195ad0535657150b7d5d9.zip gdb-e57ed3695a65ecbc76c195ad0535657150b7d5d9.tar.gz gdb-e57ed3695a65ecbc76c195ad0535657150b7d5d9.tar.bz2 | |
RISC-V: Add support for 'Zvfh' and 'Zvfhmin'
This commit adds support for recently ratified vector FP16 extensions:
'Zvfh' and 'Zvfhmin'.
This is based on:
<https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#zvfhmin-vector-extension-for-minimal-half-precision-floating-point>
<https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#zvfh-vector-extension-for-half-precision-floating-point>
Despite not having any new instructions, it will be necessary since those
extensions are already implemented in GCC.
Note that however, in this commit, following dependencies are implemented.
1. 'Zvfhmin' -> 'Zve32f'
2. 'Zvfh' -> 'Zvfhmin' (not 'Zvfh' -> 'Zve32f' as in the documentation)
3. 'Zvfh' -> 'Zfhmin'
This is because the instructions and configurations supported by the
'Zvfh' extension is a strict superset of the 'Zvfhmin' extension and
'Zvfh' -> 'Zve32f' dependency is indirectly derived from that fact.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_implicit_subsets): Add implications
related to 'Zvfh' and 'Zvfhmin' extensions.
(riscv_supported_std_z_ext) Add 'Zvfh' and 'Zvfhmin' to the list.
Diffstat (limited to 'bfd')
| -rw-r--r-- | bfd/elfxx-riscv.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 2ce95d9..ee45987 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1110,6 +1110,9 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"v", "d", check_implicit_always}, {"v", "zve64d", check_implicit_always}, {"v", "zvl128b", check_implicit_always}, + {"zvfh", "zvfhmin", check_implicit_always}, + {"zvfh", "zfhmin", check_implicit_always}, + {"zvfhmin", "zve32f", check_implicit_always}, {"zve64d", "d", check_implicit_always}, {"zve64d", "zve64f", check_implicit_always}, {"zve64f", "zve32f", check_implicit_always}, @@ -1287,6 +1290,8 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = {"zve64d", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvbc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvfh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvfhmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvkg", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvkn", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvkng", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, |