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authorTsukasa OI <research_trasio@irq.a4lg.com>2022-01-11 19:14:02 +0900
committerNelson Chu <nelson.chu@sifive.com>2022-03-18 15:32:16 +0800
commit3b374308d3006407b9571e573e4ccce4e904a4c4 (patch)
tree96bfce86a830f793e0ef73924c4b3c1b3788b68a /bfd
parent5fac3f02edacfca458f7eeaaaa33a87e26e0e332 (diff)
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RISC-V: Prefetch hint instructions and operand set
This commit adds 'Zicbop' hint instructions. bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add handling for new instruction class. gas/ChangeLog: * config/tc-riscv.c (riscv_ip): Add handling for new operand type 'f' (32-byte aligned pseudo S-type immediate for prefetch hints). (validate_riscv_insn): Likewise. include/ChangeLog: * opcode/riscv-opc.h (MATCH_PREFETCH_I, MASK_PREFETCH_I, MATCH_PREFETCH_R, MASK_PREFETCH_R, MATCH_PREFETCH_W, MASK_PREFETCH_W): New macros. * opcode/riscv.h (enum riscv_insn_class): Add new instruction class INSN_CLASS_ZICBOP. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Add handling for new operand type. * riscv-opc.c (riscv_opcodes): Add prefetch hint instructions.
Diffstat (limited to 'bfd')
-rw-r--r--bfd/elfxx-riscv.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 2915b74..185bab7 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1172,6 +1172,7 @@ static struct riscv_supported_ext riscv_supported_std_ext[] =
static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{
+ {"zicbop", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zicsr", ISA_SPEC_CLASS_20191213, 2, 0, 0 },
{"zicsr", ISA_SPEC_CLASS_20190608, 2, 0, 0 },
{"zifencei", ISA_SPEC_CLASS_20191213, 2, 0, 0 },
@@ -2316,6 +2317,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
{
case INSN_CLASS_I:
return riscv_subset_supports (rps, "i");
+ case INSN_CLASS_ZICBOP:
+ return riscv_subset_supports (rps, "zicbop");
case INSN_CLASS_ZICSR:
return riscv_subset_supports (rps, "zicsr");
case INSN_CLASS_ZIFENCEI: