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author | Maciej W. Rozycki <macro@imgtec.com> | 2017-04-25 11:44:29 +0100 |
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committer | Maciej W. Rozycki <macro@imgtec.com> | 2017-04-25 11:55:34 +0100 |
commit | 6e3d1f0728d980a384c5aa63ce7f2ff3919c5024 (patch) | |
tree | 131f83b92152d6710c91c9112b8cc07252438c58 /bfd/verilog.c | |
parent | adc1273cb27286452ed8b32c5ca3ea263b4854f0 (diff) | |
download | gdb-6e3d1f0728d980a384c5aa63ce7f2ff3919c5024.zip gdb-6e3d1f0728d980a384c5aa63ce7f2ff3919c5024.tar.gz gdb-6e3d1f0728d980a384c5aa63ce7f2ff3919c5024.tar.bz2 |
MIPS16/opcodes: Annotate instruction aliases
Complement commit 986e18a5a9fd ("Add a second 'pinfo' member to
mips_opcode to extend number of available bits"),
<https://sourceware.org/ml/binutils/2005-01/msg00261.html>, and annotate
MIPS16 NOP, LA, DLA and the synthetic forms of LD and LW instructions as
aliases. These correspond to MOVE, and the PC-relative ADDIU, DADDIU,
LD and LW hardware instructions respectively.
binutils/
* testsuite/binutils-all/mips/mips16-alias.d: New test.
* testsuite/binutils-all/mips/mips16-noalias.d: New test.
* testsuite/binutils-all/mips/mips16-alias.s: New test source.
* testsuite/binutils-all/mips/mips.exp: Run the new tests.
opcodes/
* mips16-opc.c (AL): New macro.
(mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
of "ld" and "lw" as aliases.
Diffstat (limited to 'bfd/verilog.c')
0 files changed, 0 insertions, 0 deletions