diff options
| author | Nelson Chu <nelson.chu@sifive.com> | 2024-11-20 16:30:39 +0800 |
|---|---|---|
| committer | Nelson Chu <nelson@rivosinc.com> | 2024-11-22 09:56:54 +0800 |
| commit | 595e49a4b7c6769ef23a2573148db72872c61935 (patch) | |
| tree | 4cb033daf7e71ae46317ed497db4e9260fe66d93 /bfd/elfxx-riscv.c | |
| parent | 87480dcfb62faa25b9fc6e46ae58a090ac2e43dc (diff) | |
| download | gdb-595e49a4b7c6769ef23a2573148db72872c61935.zip gdb-595e49a4b7c6769ef23a2573148db72872c61935.tar.gz gdb-595e49a4b7c6769ef23a2573148db72872c61935.tar.bz2 | |
RISC-V: Support SiFive extensions: xsfvqmaccdod, xsfvqmaccqoq and xsfvfnrclipxfqf
Those SiFive extensions have been published on the web for a while, and we plan
to implement intrinsics in GCC for those instructions soon.
NOTE: The original patch was written by Nelson when he was still working at
SiFive, and Kito rebased it to the trunk. Therefore, I kept the author as Nelson
with his SiFive email.
Document links:
xsfvqmaccdod: https://www.sifive.com/document-file/sifive-int8-matrix-multiplication-extensions-specification
xsfvqmaccqoq: https://www.sifive.com/document-file/sifive-int8-matrix-multiplication-extensions-specification
xsfvfnrclipxfqf: https://www.sifive.com/document-file/fp32-to-int8-ranged-clip-instructions
Co-authored-by: Kito Cheng <kito.cheng@sifive.com>
Diffstat (limited to 'bfd/elfxx-riscv.c')
| -rw-r--r-- | bfd/elfxx-riscv.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 701c724..45da83e 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1187,6 +1187,11 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"a", "+zaamo,+zalrsc", check_implicit_always}, {"xsfvcp", "+zve32x", check_implicit_always}, + {"xsfvqmaccqoq", "+zve32x,+zvl256b", check_implicit_always}, + {"xsfvqmaccqoq", "+zvl256b", check_implicit_always}, + {"xsfvqmaccdod", "+zve32x,+zvl128b", check_implicit_always}, + {"xsfvfnrclipxfqf", "+zve32f", check_implicit_always}, + {"v", "+zve64d,+zvl128b", check_implicit_always}, {"zvfh", "+zvfhmin,+zfhmin", check_implicit_always}, {"zvfhmin", "+zve32f", check_implicit_always}, @@ -1493,6 +1498,9 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] = {"xventanacondops", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xsfvcp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xsfcease", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"xsfvqmaccqoq", ISA_SPEC_CLASS_DRAFT, 1, 0, 0}, + {"xsfvqmaccdod", ISA_SPEC_CLASS_DRAFT, 1, 0, 0}, + {"xsfvfnrclipxfqf", ISA_SPEC_CLASS_DRAFT, 1, 0, 0}, {NULL, 0, 0, 0, 0} }; @@ -2776,6 +2784,12 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, return riscv_subset_supports (rps, "xsfvcp"); case INSN_CLASS_XSFCEASE: return riscv_subset_supports (rps, "xsfcease"); + case INSN_CLASS_XSFVQMACCQOQ: + return riscv_subset_supports (rps, "xsfvqmaccqoq"); + case INSN_CLASS_XSFVQMACCDOD: + return riscv_subset_supports (rps, "xsfvqmaccdod"); + case INSN_CLASS_XSFVFNRCLIPXFQF: + return riscv_subset_supports (rps, "xsfvfnrclipxfqf"); default: rps->error_handler (_("internal: unreachable INSN_CLASS_*")); |