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authorJeff Law <law@redhat.com>1998-07-24 17:49:08 +0000
committerJeff Law <law@redhat.com>1998-07-24 17:49:08 +0000
commit88ac1a5e137356d81e07149f23f3e4f7eaa76c7f (patch)
treef92256bb07fce8a633b8c290bbebec9057ccda4d /bfd/elf-m10300.c
parent06992a452a720f68653fcc5b4ebd3b4cad6ce031 (diff)
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* elf-m10300.c (mn10300_elf_relax_section): Do not relax "dmul",
"dmulu", "dmach", "dmachu" with 32bit operands.
Diffstat (limited to 'bfd/elf-m10300.c')
-rw-r--r--bfd/elf-m10300.c12
1 files changed, 8 insertions, 4 deletions
diff --git a/bfd/elf-m10300.c b/bfd/elf-m10300.c
index 6601447..cd7dd5f1 100644
--- a/bfd/elf-m10300.c
+++ b/bfd/elf-m10300.c
@@ -1897,7 +1897,7 @@ mn10300_elf_relax_section (abfd, sec, link_info, again)
bfd_vma value = symval;
value += irel->r_addend;
- /* See if the value will fit in 8 bits.
+ /* See if the value will fit in 8 bits. */
if ((long)value < 0x7f && (long)value > -0x80)
{
unsigned char code;
@@ -1913,9 +1913,13 @@ mn10300_elf_relax_section (abfd, sec, link_info, again)
/* Get the second opcode. */
code = bfd_get_8 (abfd, contents + irel->r_offset - 2);
- if ((code & 0x0f) == 0x09 || (code & 0x0f) == 0x08
- || (code & 0x0f) == 0x0a || (code & 0x0f) == 0x0b
- || (code & 0x0f) == 0x0e)
+ /* We can not relax 0x6b, 0x7b, 0x8b, 0x9b as no 24bit
+ equivalent instructions exists. */
+ if (code != 0x6b && code != 0x7b
+ && code != 0x8b && code != 0x9b
+ && ((code & 0x0f) == 0x09 || (code & 0x0f) == 0x08
+ || (code & 0x0f) == 0x0a || (code & 0x0f) == 0x0b
+ || (code & 0x0f) == 0x0e))
{
/* Not safe if the high bit is on as relaxing may
move the value out of high mem and thus not fit