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authorIan Lance Taylor <ian@airs.com>1996-08-30 22:09:51 +0000
committerIan Lance Taylor <ian@airs.com>1996-08-30 22:09:51 +0000
commitc86158e591edd8450f49f8cd75f82e4313d4b6d8 (patch)
treee17ece37589761df543fb981c2c1dd6391dab4e5 /bfd/bfd-in2.h
parent787d66bb4d1d8ded6de1a1f3bf7b3d32ec516b20 (diff)
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Add SH ELF support.
* elf32-sh.c: New file. * elf.c (prep_headers): Handle bfd_arch_sh. * elfcode.h (write_relocs): Handle absolute symbol. * elf-bfd.h (_bfd_elf32_link_read_relocs): Declare. (_bfd_elf64_link_read_relocs): Declare. * elflink.h (NAME(_bfd_elf,link_read_relocs)): Rename from elf_link_read_relocs. Make globally visible. Change all callers. (elf_link_input_bfd): Get external symbols from cache in symtab_hdr->contents. Get contents from cache in elf_section_data. * elfxx-target.h (bfD_elfNN_bfd_relax_section): Only define if not already defined. * reloc.c: Define BFD_RELOC_SH_* relocs. * libbfd-in.h (_bfd_sh_align_load_span): Declare. * coff-sh.c (sh_insns_conflict): Fix a return value. (_bfd_sh_align_load_span): New globally visible function, broken out of sh_align_load. (sh_align_load): Call _bfd_sh_align_load_span. (sh_swap_insns): Change relocs parameter to PTR. * bfd-in2.h, libbfd.h: Rebuild. * targets.c (bfd_elf32_sh_vec): Declare. (bfd_elf32_shl_vec): Declare. * config.bfd (sh-*-elf*): New target. * configure.in (bfd_elf32_sh_vec): New target vector. (bfd_elf32_shl_vec): New target vector. * configure: Rebuild. * Makefile.in: Rebuild dependencies. (BFD32_BACKENDS): Add elf32-sh.o. (BFD32_BACKENDS_CFILES): Add elf32-sh.c. * elf.c (map_sections_to_segments): Check that LMA does not skip a page before checking D_PAGED.
Diffstat (limited to 'bfd/bfd-in2.h')
-rw-r--r--bfd/bfd-in2.h31
1 files changed, 31 insertions, 0 deletions
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index f4c273f..0ab5432 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -1216,6 +1216,9 @@ enum bfd_architecture
bfd_arch_arm, /* Advanced Risc Machines ARM */
bfd_arch_ns32k, /* National Semiconductors ns32000 */
bfd_arch_w65, /* WDC 65816 */
+ /* start-sanitize-v850 */
+ bfd_arch_v850, /* NEC V850 */
+ /* end-sanitize-v850 */
/* start-sanitize-arc */
bfd_arch_arc, /* Argonaut RISC Core */
#define bfd_mach_arc_base 0
@@ -1765,6 +1768,30 @@ not stored in the instruction. */
BFD_RELOC_ARM_IN_POOL,
BFD_RELOC_ARM_OFFSET_IMM8,
BFD_RELOC_ARM_HWLITERAL,
+ BFD_RELOC_ARM_THUMB_ADD,
+ BFD_RELOC_ARM_THUMB_IMM,
+ BFD_RELOC_ARM_THUMB_SHIFT,
+ BFD_RELOC_ARM_THUMB_OFFSET,
+
+/* Hitachi SH relocs. Not all of these appear in object files. */
+ BFD_RELOC_SH_PCDISP8BY2,
+ BFD_RELOC_SH_PCDISP12BY2,
+ BFD_RELOC_SH_IMM4,
+ BFD_RELOC_SH_IMM4BY2,
+ BFD_RELOC_SH_IMM4BY4,
+ BFD_RELOC_SH_IMM8,
+ BFD_RELOC_SH_IMM8BY2,
+ BFD_RELOC_SH_IMM8BY4,
+ BFD_RELOC_SH_PCRELIMM8BY2,
+ BFD_RELOC_SH_PCRELIMM8BY4,
+ BFD_RELOC_SH_SWITCH16,
+ BFD_RELOC_SH_SWITCH32,
+ BFD_RELOC_SH_USES,
+ BFD_RELOC_SH_COUNT,
+ BFD_RELOC_SH_ALIGN,
+ BFD_RELOC_SH_CODE,
+ BFD_RELOC_SH_DATA,
+ BFD_RELOC_SH_LABEL,
/* start-sanitize-arc */
/* Argonaut RISC Core (ARC) relocs.
@@ -1802,6 +1829,10 @@ assumed to be 0. */
BFD_RELOC_D10V_18_PCREL,
/* end-sanitize-d10v */
+/* NEC V850 relocs. */
+ BFD_RELOC_V850_9_PCREL,
+ BFD_RELOC_V850_22_PCREL,
+
BFD_RELOC_UNUSED };
typedef enum bfd_reloc_code_real bfd_reloc_code_real_type;
reloc_howto_type *