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| author | Tsukasa OI <research_trasio@irq.a4lg.com> | 2022-09-05 07:54:51 +0000 |
|---|---|---|
| committer | Tsukasa OI <research_trasio@irq.a4lg.com> | 2022-09-09 10:12:13 +0000 |
| commit | 1daabcc746e7d2f04ab190b49aec9abb020f29aa (patch) | |
| tree | 30c0cd81c436cd6363b27cf0540e80fb9576ba1a /bfd/ChangeLog | |
| parent | 58448ad29c213deb605908096833b191e09745eb (diff) | |
| download | gdb-1daabcc746e7d2f04ab190b49aec9abb020f29aa.zip gdb-1daabcc746e7d2f04ab190b49aec9abb020f29aa.tar.gz gdb-1daabcc746e7d2f04ab190b49aec9abb020f29aa.tar.bz2 | |
RISC-V: Fix vector CSR requirements
Vector CSRs are also required on smaller vector subsets.
Not only that the most of vector CSRs are general purpose (and must be
accessible for every vector subsets), current minimum vector subset 'Zve32x'
requires fixed point arithmetic, making remaining non-general purpose
(fixed point arithmetic only) CSRs mandatory for such subsets.
So, those CSRs must be accessible from 'Zve32x', not just from 'V'.
This commit fixes this issue which caused CSR accessibility warnings.
gas/ChangeLog:
* config/tc-riscv.c (riscv_csr_address): Change vector CSR
requirement from 'V' to 'Zve32x'.
* testsuite/gas/riscv/csr-version-1p9p1.l: Change vector CSR
requirement from 'V' to 'Zve32x'.
* testsuite/gas/riscv/csr-version-1p10.l: Likewise.
* testsuite/gas/riscv/csr-version-1p11.l: Likewise.
* testsuite/gas/riscv/csr-version-1p12.l: Likewise.
Diffstat (limited to 'bfd/ChangeLog')
0 files changed, 0 insertions, 0 deletions