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author | Matthew Malcomson <matthew.malcomson@arm.com> | 2018-11-06 14:52:11 +0000 |
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committer | Richard Earnshaw <Richard.Earnshaw@arm.com> | 2018-11-06 14:54:32 +0000 |
commit | bc52d49c1d0e9b5d196132efb41addaf0bddad4f (patch) | |
tree | 28574505e5caa02d1c8d9270cdbe241ddbffd710 /Makefile.tpl | |
parent | 0632eeea6eb1096fe7ddbd7f81bd74b360d1f511 (diff) | |
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[arm] Check for neon and condition in vcvt.f16.f32
VCVT between f16 and f32 is an Advanced SIMD instruction.
Not all the VCVT alternatives need neon, hence the check for neon is in
the encode function.
The check on neon for VCVT.f16.f32 (and vice versa) is missing.
vshcmd: > echo 'vcvt.f16.f32 d1, q1' | gas/as-new -mfpu=vfpxd -march=armv8.5-a -
testdir [15:59:10] $
Also, the handling of the condition code behaves differently to other
SIMD instructions -- no error message is produced when assembling an
instruction with a condition code suffix despite the arm encoding not
allowing a condition code. (n.b. the actual binary produced is
independent of the suffix).
The instruction should be treated similarly to VSUBL that has the same
caveat of "must be unconditional" describing the {<c>} symbol. vcvt
half-precision to single precision found in F6.1.58 in the ARM
Architecture Reference Manual issue C.a, vsubl found in F6.1.240 in
the ARM Architecture Reference Manual issue C.a
2018-11-06 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-arm.c (do_neon_cvt_1): Add check for neon and condition
codes to half-precision conversion.
* testsuite/gas/arm/neon-cond-bad-inc.s: Check vcvteq disallowed.
* testsuite/gas/arm/neon-cond-bad.l: Likewise.
* testsuite/gas/arm/neon-cond-bad_t2.d: Check vcvteq allowed in IT
block.
* testsuite/gas/arm/vfp-bad.l: Ensure vcvt doesn't work without neon.
* testsuite/gas/arm/vfp-bad.s: Likewise.
Diffstat (limited to 'Makefile.tpl')
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