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author | Jin Ma <jinma@linux.alibaba.com> | 2023-11-18 15:04:50 +0800 |
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committer | Nelson Chu <nelson@rivosinc.com> | 2023-11-23 09:31:38 +0800 |
commit | 0bd0e6522a8763828d8ff6e5886ebd7fd14141e0 (patch) | |
tree | bfffdf771fc5562f6143eae67d09370e6e3a1f06 /COPYING.NEWLIB | |
parent | 9aa5dde64d7bad3f405d42ac8c25b91775864178 (diff) | |
download | gdb-0bd0e6522a8763828d8ff6e5886ebd7fd14141e0.zip gdb-0bd0e6522a8763828d8ff6e5886ebd7fd14141e0.tar.gz gdb-0bd0e6522a8763828d8ff6e5886ebd7fd14141e0.tar.bz2 |
RISC-V: Add load/store instructions for T-Head VECTOR vendor extension
T-Head has a range of vendor-specific instructions. Therefore
it makes sense to group them into smaller chunks in form of
vendor extensions.
This patch adds load/store instructions for the "XTheadVector"
extension. The 'th' prefix and the "XTheadVector" extension are
documented in a PR for the RISC-V toolchain conventions ([1]).
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>
gas/ChangeLog:
* testsuite/gas/riscv/x-thead-vector.d: Add tests for
load/store instructions.
* testsuite/gas/riscv/x-thead-vector.s: Likewise.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_TH_VLBV): New.
opcodes/ChangeLog:
* riscv-opc.c: Likewise.
Diffstat (limited to 'COPYING.NEWLIB')
0 files changed, 0 insertions, 0 deletions