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| author | Andrew Carlotti <andrew.carlotti@arm.com> | 2024-01-12 01:45:57 +0000 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2024-01-12 13:46:35 +0000 |
| commit | f6cfacfed1fd604bea8fd95324f245e10a322320 (patch) | |
| tree | 955a6fc4ebaf5625bc59cff60ef9476a3c2deeb3 | |
| parent | 43291582c0bcd2a6b7b658ee61753f55f9682c70 (diff) | |
| download | gdb-f6cfacfed1fd604bea8fd95324f245e10a322320.zip gdb-f6cfacfed1fd604bea8fd95324f245e10a322320.tar.gz gdb-f6cfacfed1fd604bea8fd95324f245e10a322320.tar.bz2 | |
aarch64: Make FEAT_ASMv8p2 instruction aliases always available
There's no reason to disallow the aliases when the aliased instructions are
always available. The new behaviour matches existing LLVM behaviour.
| -rw-r--r-- | gas/testsuite/gas/aarch64/alias-2.d | 2 | ||||
| -rw-r--r-- | opcodes/aarch64-tbl.h | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/gas/testsuite/gas/aarch64/alias-2.d b/gas/testsuite/gas/aarch64/alias-2.d index 45ddcf5..610382b 100644 --- a/gas/testsuite/gas/aarch64/alias-2.d +++ b/gas/testsuite/gas/aarch64/alias-2.d @@ -1,5 +1,5 @@ #objdump: -dr -#as: -march=armv8.2-a +#as: -march=armv8-a .*: file format .* diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 95f7757..3df273c 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -3572,7 +3572,7 @@ const struct aarch64_opcode aarch64_opcode_table[] = CORE_INSN ("asr", 0x13000000, 0x7f800000, bitfield, OP_ASR_IMM, OP3 (Rd, Rn, IMM), QL_SHIFT, F_ALIAS | F_P2 | F_CONV), CORE_INSN ("bfm", 0x33000000, 0x7f800000, bitfield, 0, OP4 (Rd, Rn, IMMR, IMMS), QL_BF, F_HAS_ALIAS | F_SF | F_N), CORE_INSN ("bfi", 0x33000000, 0x7f800000, bitfield, OP_BFI, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV), - V8_2A_INSN ("bfc", 0x330003e0, 0x7f8003e0, bitfield, OP_BFC, OP3 (Rd, IMM, WIDTH), QL_BF1, F_ALIAS | F_P2 | F_CONV), + CORE_INSN ("bfc", 0x330003e0, 0x7f8003e0, bitfield, OP_BFC, OP3 (Rd, IMM, WIDTH), QL_BF1, F_ALIAS | F_P2 | F_CONV), CORE_INSN ("bfxil", 0x33000000, 0x7f800000, bitfield, OP_BFXIL, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV), CORE_INSN ("ubfm", 0x53000000, 0x7f800000, bitfield, 0, OP4 (Rd, Rn, IMMR, IMMS), QL_BF, F_HAS_ALIAS | F_SF | F_N), CORE_INSN ("ubfiz", 0x53000000, 0x7f800000, bitfield, OP_UBFIZ, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV), @@ -3645,7 +3645,7 @@ const struct aarch64_opcode aarch64_opcode_table[] = CORE_INSN ("rev16", 0x5ac00400, 0x7ffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAME, F_SF), CORE_INSN ("rev", 0x5ac00800, 0xfffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAMEW, 0), CORE_INSN ("rev", 0xdac00c00, 0xfffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAMEX, F_SF | F_HAS_ALIAS | F_P1), - V8_2A_INSN ("rev64", 0xdac00c00, 0xfffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAMEX, F_SF | F_ALIAS), + CORE_INSN ("rev64", 0xdac00c00, 0xfffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAMEX, F_SF | F_ALIAS), CORE_INSN ("clz", 0x5ac01000, 0x7ffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAME, F_SF), CORE_INSN ("cls", 0x5ac01400, 0x7ffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAME, F_SF), CORE_INSN ("rev32", 0xdac00800, 0xfffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAMEX, 0), |