Add support for .extCondCode, .extCoreRegister and .extAuxRegister.

gas/
2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>

	* testsuite/gas/arc/textauxregister.d: New file.
	* testsuite/gas/arc/textauxregister.s: Likewise.
	* testsuite/gas/arc/textcondcode.d: Likewise.
	* testsuite/gas/arc/textcondcode.s: Likewise.
	* testsuite/gas/arc/textcoreregister.d: Likewise.
	* testsuite/gas/arc/textcoreregister.s: Likewise.
	* testsuite/gas/arc/textpseudoop.d: Likewise.
	* testsuite/gas/arc/textpseudoop.s: Likewise.
	* testsuite/gas/arc/ld2.d: Update test.
	* testsuite/gas/arc/st.d: Likewise.
	* testsuite/gas/arc/taux.d: Likewise.
	* doc/c-arc.texi (ARC Directives): Add .extCondCode,
	.extCoreRegister and .extAuxRegister documentation.
	* config/tc-arc.c (arc_extcorereg): New function.
	(md_pseudo_table): Add .extCondCode, .extCoreRegister and
	.extAuxRegister pseudo-ops.
	(extRegister_t): New type.
	(ext_condcode, arc_aux_hash): New global variable.
	(find_opcode_match): Check for extensions.
	(preprocess_operands): Likewise.
	(md_begin): Add aux registers in a hash.
	(assemble_insn): Update use arc_flags member.
	(tokenize_extregister): New function.
	(create_extcore_section): Likewise.
	* config/tc-arc.h (MAX_FLAG_NAME_LENGHT): Increase to 10.
	(arc_flags): Delete code, add flgp.

include/
2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>

	* opcode/arc.h (flag_class_t): Update.
	(ARC_OPCODE_NONE): Define.
	(ARC_OPCODE_ARCALL): Likewise.
	(ARC_OPCODE_ARCFPX): Likewise.
	(ARC_REGISTER_READONLY): Likewise.
	(ARC_REGISTER_WRITEONLY): Likewise.
	(ARC_REGISTER_NOSHORT_CUT): Likewise.
	(arc_aux_reg): Add cpu.

opcodes/
2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>

	* arc-dis.c (find_format): Check for extension flags.
	(print_flags): New function.
	(print_insn_arc): Update for .extCondCode, .extCoreRegister and
	.extAuxRegister.
	* arc-ext.c (arcExtMap_coreRegName): Use
	LAST_EXTENSION_CORE_REGISTER.
	(arcExtMap_coreReadWrite): Likewise.
	(dump_ARC_extmap): Update printing.
	* arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
	(arc_aux_regs): Add cpu field.
	* arc-regs.h: Add cpu field, lower case name aux registers.

Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>

23 files changed, 1115 insertions, 477 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 5f93283..827130f 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,33 @@
 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 
+	* testsuite/gas/arc/textauxregister.d: New file.
+	* testsuite/gas/arc/textauxregister.s: Likewise.
+	* testsuite/gas/arc/textcondcode.d: Likewise.
+	* testsuite/gas/arc/textcondcode.s: Likewise.
+	* testsuite/gas/arc/textcoreregister.d: Likewise.
+	* testsuite/gas/arc/textcoreregister.s: Likewise.
+	* testsuite/gas/arc/textpseudoop.d: Likewise.
+	* testsuite/gas/arc/textpseudoop.s: Likewise.
+	* testsuite/gas/arc/ld2.d: Update test.
+	* testsuite/gas/arc/st.d: Likewise.
+	* testsuite/gas/arc/taux.d: Likewise.
+	* doc/c-arc.texi (ARC Directives): Add .extCondCode,
+	.extCoreRegister and .extAuxRegister documentation.
+	* config/tc-arc.c (arc_extcorereg): New function.
+	(md_pseudo_table): Add .extCondCode, .extCoreRegister and
+	.extAuxRegister pseudo-ops.
+	(extRegister_t): New type.
+	(ext_condcode, arc_aux_hash): New global variable.
+	(find_opcode_match): Check for extensions.
+	(preprocess_operands): Likewise.
+	(md_begin): Add aux registers in a hash.
+	(assemble_insn): Update use arc_flags member.
+	(tokenize_extregister): New function.
+	(create_extcore_section): Likewise.
+	* config/tc-arc.h (arc_flags): Delete code, add flgp.
+
+2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
+
 	* testsuite/gas/arc/noargs_a7.d: New file.
 	* testsuite/gas/arc/noargs_a7.s: Likewise.
 	* testsuite/gas/arc/noargs_hs.d: Likewise.
diff --git a/gas/NEWS b/gas/NEWS
index a627028..2f5e88d 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,4 +1,8 @@
 -*- text -*-
+* ARC backend accepts .extInstruction, .extCondCode, .extAuxRegister, and
+  .extCoreRegister pseudo-ops that allow an user to define custom
+  instructions, conditional codes, auxiliary and core registers.
+
 * Add a configure option --enable-elf-stt-common to decide whether ELF
   assembler should generate common symbols with the STT_COMMON type by
   default.  Default to no.
diff --git a/gas/config/tc-arc.c b/gas/config/tc-arc.c
index 3aeedb1..7486924 100644
--- a/gas/config/tc-arc.c
+++ b/gas/config/tc-arc.c
@@ -140,6 +140,7 @@ static void arc_lcomm (int);
 static void arc_option (int);
 static void arc_extra_reloc (int);
 static void arc_extinsn (int);
+static void arc_extcorereg (int);
 
 const pseudo_typeS md_pseudo_table[] =
 {
@@ -151,7 +152,10 @@ const pseudo_typeS md_pseudo_table[] =
   { "lcommon", arc_lcomm, 0 },
   { "cpu",     arc_option, 0 },
 
-  { "extinstruction", arc_extinsn, 0 },
+  { "extinstruction",  arc_extinsn, 0 },
+  { "extcoreregister", arc_extcorereg, EXT_CORE_REGISTER },
+  { "extauxregister",  arc_extcorereg, EXT_AUX_REGISTER },
+  { "extcondcode",     arc_extcorereg, EXT_COND_CODE },
 
   { "tls_gd_ld",   arc_extra_reloc, BFD_RELOC_ARC_TLS_GD_LD },
   { "tls_gd_call", arc_extra_reloc, BFD_RELOC_ARC_TLS_GD_CALL },
@@ -343,6 +347,21 @@ static const attributes_t syntaxclassmod[] =
   { "OP1_MUST_BE_IMM" , 15, ARC_OP1_MUST_BE_IMM }
 };
 
+/* Extension register type.  */
+typedef struct
+{
+  char *name;
+  int  number;
+  int  imode;
+} extRegister_t;
+
+/* A structure to hold the additional conditional codes.  */
+static struct
+{
+  struct arc_flag_operand *arc_ext_condcode;
+  int size;
+} ext_condcode = { NULL, 0 };
+
 /* Structure to hold an entry in ARC_OPCODE_HASH.  */
 struct arc_opcode_hash_entry
 {
@@ -386,6 +405,9 @@ static struct hash_control *arc_opcode_hash;
 /* The hash table of register symbols.  */
 static struct hash_control *arc_reg_hash;
 
+/* The hash table of aux register symbols.  */
+static struct hash_control *arc_aux_hash;
+
 /* A table of CPU names and opcode sets.  */
 static const struct cpu_type
 {
@@ -1658,31 +1680,23 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry,
 		case O_symbol:
 		  {
 		    const char *p;
-		    size_t len;
 		    const struct arc_aux_reg *auxr;
-		    unsigned j;
 
 		    if (opcode->class != AUXREG)
 		      goto de_fault;
 		    p = S_GET_NAME (tok[tokidx].X_add_symbol);
-		    len = strlen (p);
-
-		    auxr = &arc_aux_regs[0];
-		    for (j = 0; j < arc_num_aux_regs; j++, auxr++)
-		      if (len == auxr->length
-			  && strcasecmp (auxr->name, p) == 0
-                          && ((auxr->subclass == NONE)
-                              || check_cpu_feature (auxr->subclass)))
-			{
-			  /* We modify the token array here, safe in the
-			     knowledge, that if this was the wrong choice
-			     then the original contents will be restored
-			     from BKTOK.  */
-			  tok[tokidx].X_op = O_constant;
-			  tok[tokidx].X_add_number = auxr->address;
-			  ARC_SET_FLAG (tok[tokidx].X_add_symbol, ARC_FLAG_AUX);
-			  break;
-			}
+
+		    auxr = hash_find (arc_aux_hash, p);
+		    if (auxr)
+		      {
+			/* We modify the token array here, safe in the
+			   knowledge, that if this was the wrong
+			   choice then the original contents will be
+			   restored from BKTOK.  */
+			tok[tokidx].X_op = O_constant;
+			tok[tokidx].X_add_number = auxr->address;
+			ARC_SET_FLAG (tok[tokidx].X_add_symbol, ARC_FLAG_AUX);
+		      }
 
 		    if (tok[tokidx].X_op != O_constant)
 		      goto de_fault;
@@ -1809,7 +1823,7 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry,
       /* Setup ready for flag parsing.  */
       lnflg = nflgs;
       for (i = 0; i < nflgs; i++)
-        first_pflag [i].code = 0;
+	first_pflag[i].flgp = NULL;
 
       /* Check the flags.  Iterate over the valid flag classes.  */
       for (flgidx = opcode->flags; *flgidx; ++flgidx)
@@ -1818,31 +1832,57 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry,
 	  const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx];
 	  const unsigned *flgopridx;
 	  int cl_matches = 0;
+	  struct arc_flags *pflag = NULL;
+
+	  /* Check for extension conditional codes.  */
+	  if (ext_condcode.arc_ext_condcode
+	      && cl_flags->class & F_CLASS_EXTEND)
+	    {
+	      struct arc_flag_operand *pf = ext_condcode.arc_ext_condcode;
+	      while (pf->name)
+		{
+		  pflag = first_pflag;
+		  for (i = 0; i < nflgs; i++, pflag++)
+		    {
+		      if (!strcmp (pf->name, pflag->name))
+			{
+			  if (pflag->flgp != NULL)
+			    goto match_failed;
+			  /* Found it.  */
+			  cl_matches++;
+			  pflag->flgp = pf;
+			  lnflg--;
+			  break;
+			}
+		    }
+		  pf++;
+		}
+	    }
 
 	  for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx)
 	    {
 	      const struct arc_flag_operand *flg_operand;
-	      struct arc_flags *pflag = first_pflag;
 
+	      pflag = first_pflag;
 	      flg_operand = &arc_flag_operands[*flgopridx];
 	      for (i = 0; i < nflgs; i++, pflag++)
 		{
 		  /* Match against the parsed flags.  */
 		  if (!strcmp (flg_operand->name, pflag->name))
 		    {
-		      if (pflag->code != 0)
+		      if (pflag->flgp != NULL)
 			goto match_failed;
 		      cl_matches++;
-		      pflag->code = *flgopridx;
+		      pflag->flgp = (struct arc_flag_operand *) flg_operand;
 		      lnflg--;
 		      break; /* goto next flag class and parsed flag.  */
 		    }
 		}
 	    }
 
-	  if (cl_flags->class == F_CLASS_REQUIRED && cl_matches == 0)
+	  if ((cl_flags->class & F_CLASS_REQUIRED) && cl_matches == 0)
 	    goto match_failed;
-	  if (cl_flags->class == F_CLASS_OPTIONAL && cl_matches > 1)
+	  if ((cl_flags->class & F_CLASS_OPTIONAL) && cl_matches > 1)
 	    goto match_failed;
 	}
       /* Did I check all the parsed flags?  */
@@ -2345,6 +2385,30 @@ md_begin (void)
 
   /* Initialize the last instructions.  */
   memset (&arc_last_insns[0], 0, sizeof (arc_last_insns));
+
+  /* Aux register declaration.  */
+  arc_aux_hash = hash_new ();
+  if (arc_aux_hash == NULL)
+    as_fatal (_("Virtual memory exhausted"));
+
+  const struct arc_aux_reg *auxr = &arc_aux_regs[0];
+  unsigned int i;
+  for (i = 0; i < arc_num_aux_regs; i++, auxr++)
+    {
+      const char *retval;
+
+      if (!(auxr->cpu & arc_target))
+	continue;
+
+      if ((auxr->subclass != NONE)
+	  && !check_cpu_feature (auxr->subclass))
+	continue;
+
+      retval = hash_insert (arc_aux_hash, auxr->name, (void *) auxr);
+      if (retval)
+	as_fatal (_("internal error: can't hash aux register '%s': %s"),
+		  auxr->name, retval);
+    }
 }
 
 /* Write a value out to the object file, using the appropriate
@@ -3631,8 +3695,7 @@ assemble_insn (const struct arc_opcode *opcode,
   /* Handle flags.  */
   for (i = 0; i < nflg; i++)
     {
-      const struct arc_flag_operand *flg_operand =
-	&arc_flag_operands[pflags[i].code];
+      const struct arc_flag_operand *flg_operand = pflags[i].flgp;
 
       /* Check if the instruction has a delay slot.  */
       if (!strcmp (flg_operand->name, "d"))
@@ -4194,6 +4257,249 @@ arc_extinsn (int ignore ATTRIBUTE_UNUSED)
   create_extinst_section (&einsn);
 }
 
+static void
+tokenize_extregister (extRegister_t *ereg, int opertype)
+{
+  char *name;
+  char *mode;
+  char c;
+  char *p;
+  int number, imode = 0;
+  bfd_boolean isCore_p = (opertype == EXT_CORE_REGISTER) ? TRUE : FALSE;
+  bfd_boolean isReg_p  = (opertype == EXT_CORE_REGISTER
+			  || opertype == EXT_AUX_REGISTER) ? TRUE : FALSE;
+
+  /* 1st: get register name.  */
+  SKIP_WHITESPACE ();
+  p = input_line_pointer;
+  c = get_symbol_name (&p);
+
+  name = xstrdup (p);
+  restore_line_pointer (c);
+
+  /* 2nd: get register number.  */
+  SKIP_WHITESPACE ();
+
+  if (*input_line_pointer != ',')
+    {
+      as_bad (_("expected comma after register name"));
+      ignore_rest_of_line ();
+      free (name);
+      return;
+    }
+  input_line_pointer++;
+  number = get_absolute_expression ();
+
+  if (number < 0)
+    {
+      as_bad (_("negative operand number %d"), number);
+      ignore_rest_of_line ();
+      free (name);
+      return;
+    }
+
+  if (isReg_p)
+    {
+      /* 3rd: get register mode.  */
+      SKIP_WHITESPACE ();
+
+      if (*input_line_pointer != ',')
+	{
+	  as_bad (_("expected comma after register number"));
+	  ignore_rest_of_line ();
+	  free (name);
+	  return;
+	}
+
+      input_line_pointer++;
+      mode = input_line_pointer;
+
+      if (!strncmp (mode, "r|w", 3))
+	{
+	  imode = 0;
+	  input_line_pointer += 3;
+	}
+      else if (!strncmp (mode, "r", 1))
+	{
+	  imode = ARC_REGISTER_READONLY;
+	  input_line_pointer += 1;
+	}
+      else if (strncmp (mode, "w", 1))
+	{
+	  as_bad (_("invalid mode"));
+	  ignore_rest_of_line ();
+	  free (name);
+	  return;
+	}
+      else
+	{
+	  imode = ARC_REGISTER_WRITEONLY;
+	  input_line_pointer += 1;
+	}
+    }
+
+  if (isCore_p)
+    {
+      /* 4th: get core register shortcut.  */
+      SKIP_WHITESPACE ();
+      if (*input_line_pointer != ',')
+	{
+	  as_bad (_("expected comma after register mode"));
+	  ignore_rest_of_line ();
+	  free (name);
+	  return;
+	}
+
+      input_line_pointer++;
+
+      if (!strncmp (input_line_pointer, "cannot_shortcut", 15))
+	{
+	  imode |= ARC_REGISTER_NOSHORT_CUT;
+	  input_line_pointer += 15;
+	}
+      else if (strncmp (input_line_pointer, "can_shortcut", 12))
+	{
+	  as_bad (_("shortcut designator invalid"));
+	  ignore_rest_of_line ();
+	  free (name);
+	  return;
+	}
+      else
+	{
+	  input_line_pointer += 12;
+	}
+    }
+  demand_empty_rest_of_line ();
+
+  ereg->name = name;
+  ereg->number = number;
+  ereg->imode  = imode;
+}
+
+/* Create an extension register/condition description in the arc
+   extension section of the output file.
+
+   The structure for an instruction is like this:
+   [0]: Length of the record.
+   [1]: Type of the record.
+
+   For core regs and condition codes:
+   [2]: Value.
+   [3]+ Name.
+
+   For auxilirary registers:
+   [2..5]: Value.
+   [6]+ Name
+
+   The sequence is terminated by an empty entry.  */
+
+static void
+create_extcore_section (extRegister_t *ereg, int opertype)
+{
+  segT old_sec   = now_seg;
+  int old_subsec = now_subseg;
+  char *p;
+  int name_len   = strlen (ereg->name);
+
+  arc_set_ext_seg ();
+
+  switch (opertype)
+    {
+    case EXT_COND_CODE:
+    case EXT_CORE_REGISTER:
+      p = frag_more (1);
+      *p = 3 + name_len + 1;
+      p = frag_more (1);
+      *p = opertype;
+      p = frag_more (1);
+      *p = ereg->number;
+      break;
+    case EXT_AUX_REGISTER:
+      p = frag_more (1);
+      *p = 6 + name_len + 1;
+      p = frag_more (1);
+      *p = EXT_AUX_REGISTER;
+      p = frag_more (1);
+      *p = (ereg->number >> 24) & 0xff;
+      p = frag_more (1);
+      *p = (ereg->number >> 16) & 0xff;
+      p = frag_more (1);
+      *p = (ereg->number >>  8) & 0xff;
+      p = frag_more (1);
+      *p = (ereg->number)       & 0xff;
+      break;
+    default:
+      break;
+    }
+
+  p = frag_more (name_len + 1);
+  strcpy (p, ereg->name);
+
+  subseg_set (old_sec, old_subsec);
+}
+
+/* Handler .extCoreRegister pseudo-op.  */
+
+static void
+arc_extcorereg (int opertype)
+{
+  extRegister_t ereg;
+  struct arc_aux_reg *auxr;
+  const char *retval;
+  struct arc_flag_operand *ccode;
+
+  memset (&ereg, 0, sizeof (ereg));
+  tokenize_extregister (&ereg, opertype);
+
+  switch (opertype)
+    {
+    case EXT_CORE_REGISTER:
+      /* Core register.  */
+      if (ereg.number > 60)
+	as_bad (_("core register %s value (%d) too large"), ereg.name,
+		ereg.number);
+      declare_register (ereg.name, ereg.number);
+      break;
+    case EXT_AUX_REGISTER:
+      /* Auxiliary register.  */
+      auxr = xmalloc (sizeof (struct arc_aux_reg));
+      auxr->name = ereg.name;
+      auxr->cpu = arc_target;
+      auxr->subclass = NONE;
+      auxr->address = ereg.number;
+      retval = hash_insert (arc_aux_hash, auxr->name, (void *) auxr);
+      if (retval)
+	as_fatal (_("internal error: can't hash aux register '%s': %s"),
+		  auxr->name, retval);
+      break;
+    case EXT_COND_CODE:
+      /* Condition code.  */
+      if (ereg.number > 31)
+	as_bad (_("condition code %s value (%d) too large"), ereg.name,
+		ereg.number);
+      ext_condcode.size ++;
+      ext_condcode.arc_ext_condcode =
+	xrealloc (ext_condcode.arc_ext_condcode,
+		  (ext_condcode.size + 1) * sizeof (struct arc_flag_operand));
+      if (ext_condcode.arc_ext_condcode == NULL)
+	as_fatal (_("Virtual memory exhausted"));
+
+      ccode = ext_condcode.arc_ext_condcode + ext_condcode.size - 1;
+      ccode->name   = ereg.name;
+      ccode->code   = ereg.number;
+      ccode->bits   = 5;
+      ccode->shift  = 0;
+      ccode->favail = 0; /* not used.  */
+      ccode++;
+      memset (ccode, 0, sizeof (struct arc_flag_operand));
+      break;
+    default:
+      as_bad (_("Unknown extension"));
+      break;
+    }
+  create_extcore_section (&ereg, opertype);
+}
+
 /* Local variables:
    eval: (c-set-style "gnu")
    indent-tabs-mode: t
diff --git a/gas/config/tc-arc.h b/gas/config/tc-arc.h
index 54fa601..16f6a06 100644
--- a/gas/config/tc-arc.h
+++ b/gas/config/tc-arc.h
@@ -224,8 +224,8 @@ struct arc_flags
   /* Name of the parsed flag.  */
   char name[MAX_FLAG_NAME_LENGTH + 1];
 
-  /* The code of the parsed flag.  Valid when is not zero.  */
-  unsigned char code;
+  /* Pointer to arc flags.  */
+  struct arc_flag_operand *flgp;
 };
 
 extern const relax_typeS md_relax_table[];
diff --git a/gas/doc/c-arc.texi b/gas/doc/c-arc.texi
index a237285..a3e18cf 100644
--- a/gas/doc/c-arc.texi
+++ b/gas/doc/c-arc.texi
@@ -335,11 +335,11 @@ two.  If no alignment is specified, as will set the alignment to the
 largest power of two less than or equal to the size of the symbol, up
 to a maximum of 16.
 
-@cindex @code{lcommon} directive
+@cindex @code{lcommon} directive, ARC
 @item .lcommon @var{symbol}, @var{length}[, @var{alignment}]
 The same as @code{lcomm} directive.
 
-@cindex @code{cpu} directive
+@cindex @code{cpu} directive, ARC
 @item .cpu @var{cpu}
 The @code{.cpu} directive must be followed by the desired core
 version.  Permitted values for CPU are:
@@ -362,8 +362,84 @@ Note: the @code{.cpu} directive overrides the command line option
 @code{-mcpu=@var{cpu}}; a warning is emitted when the version is not
 consistent between the two.
 
+@item .extAuxRegister @var{name}, @var{addr}, @var{mode}
+@cindex @code{extAuxRegister} directive, ARC
+Auxiliary registers can be defined in the assembler source code by
+using this directive.  The first parameter, @var{name}, is the name of the
+new auxiliary register.  The second parameter, @var{addr}, is
+address the of the auxiliary register.  The third parameter,
+@var{mode}, specifies whether the register is readable and/or writable
+and is one of:
+@table @code
+@item r
+Read only;
+
+@item w
+Write only;
+
+@item r|w
+Read and write.
+
+@end table
+
+For example:
+@example
+	.extAuxRegister mulhi, 0x12, w
+@end example
+specifies a write only extension auxiliary register, @var{mulhi} at
+address 0x12.
+
+@item .extCondCode @var{suffix}, @var{val}
+@cindex @code{extCondCode} directive, ARC
+ARC supports extensible condition codes.  This directive defines a new
+condition code, to be known by the suffix, @var{suffix} and will
+depend on the value, @var{val} in the condition code.
+
+For example:
+@example
+	.extCondCode is_busy,0x14
+	add.is_busy  r1,r2,r3
+@end example
+will only execute the @code{add} instruction if the condition code
+value is 0x14.
+
+@item .extCoreRegister @var{name}, @var{regnum}, @var{mode}, @var{shortcut}
+@cindex @code{extCoreRegister} directive, ARC
+Specifies an extension core register named @var{name} as a synonym for
+the register numbered @var{regnum}.  The register number must be
+between 32 and 59.  The third argument, @var{mode}, indicates whether
+the register is readable and/or writable and is one of:
+@table @code
+@item r
+Read only;
+
+@item w
+Write only;
+
+@item r|w
+Read and write.
+
+@end table
+
+The final parameter, @var{shortcut} indicates whether the register has
+a short cut in the pipeline.  The valid values are:
+@table @code
+@item can_shortcut
+The register has a short cut in the pipeline;
+
+@item cannot_shortcut
+The register does not have a short cut in the pipeline.
+@end table
+
+For example:
+@example
+	.extCoreRegister mlo, 57, r , can_shortcut
+@end example
+defines a read only extension core register, @code{mlo}, which is
+register 57, and can short cut the pipeline.
+
 @item .extInstruction @var{name}, @var{opcode}, @var{subopcode}, @var{suffixclass}, @var{syntaxclass}
-@cindex @code{extInstruction} directive
+@cindex @code{extInstruction} directive, ARC
 ARC allows the user to specify extension instructions.  These
 extension instructions are not macros; the assembler creates encodings
 for use of these instructions according to the specification by the
diff --git a/gas/testsuite/gas/arc/ld2.d b/gas/testsuite/gas/arc/ld2.d
index c2f6b1f..0a7874c 100644
--- a/gas/testsuite/gas/arc/ld2.d
+++ b/gas/testsuite/gas/arc/ld2.d
@@ -15,5 +15,5 @@ Disassembly of section .text:
   1c:	130f 0082           	ldb	r2,\[r3,15\]
   20:	14fe 8103           	ld[hw]+	r3,\[r4,-2\]
   24:	212a 0080           	lr	r1,\[r2\]
-  28:	216a 0500           	lr	r1,\[0x14\]
-  2c:	206a 0000           	lr	r0,\[0\]
+  28:	216a 0500           	lr	r1,\[dmc_code_ram\]
+  2c:	206a 0000           	lr	r0,\[status\]
diff --git a/gas/testsuite/gas/arc/st.d b/gas/testsuite/gas/arc/st.d
index 4e2ebba..3f75d40 100644
--- a/gas/testsuite/gas/arc/st.d
+++ b/gas/testsuite/gas/arc/st.d
@@ -27,4 +27,4 @@ Disassembly of section .text:
   50:	262b 7080 0000 0064 	sr	0x64,\[r2\]
   58:	212b 0f80 0000 2710 	sr	r1,\[0x2710\]
   60:	266b 7fc0 0000 0064 	sr	0x64,\[0x3f\]
-  68:	26ab 7901 0000 2710 	sr	0x2710,\[100\]
+  68:	26ab 7901 0000 2710 	sr	0x2710,\[vbfdw_build\]
diff --git a/gas/testsuite/gas/arc/taux.d b/gas/testsuite/gas/arc/taux.d
index 6759d73..10f50ee 100644
--- a/gas/testsuite/gas/arc/taux.d
+++ b/gas/testsuite/gas/arc/taux.d
@@ -3,6 +3,9 @@
 #source: taux.s
 # Most of the AUX rgisters are defined for all ARC variants besides the
 # FPX/FPUDA registers which should end as undefined when assemble generic.
+.* U arc600_build_config
+.* U aux_crc_mode
+.* U aux_crc_poly
 .* U aux_dpfp1h
 .* U aux_dpfp1l
 .* U aux_dpfp2h
@@ -13,4 +16,10 @@
 .* U d2l
 .* U dpfp_status
 .* U fp_status
+.* mx0
+.* mx1
+.* my0
+.* my1
+.* scratch_a
+.* tsch
 #pass
diff --git a/gas/testsuite/gas/arc/textauxregister.d b/gas/testsuite/gas/arc/textauxregister.d
new file mode 100644
index 0000000..8a0d77e
--- /dev/null
+++ b/gas/testsuite/gas/arc/textauxregister.d
@@ -0,0 +1,12 @@
+#as: -mcpu=arcem
+#objdump: -dr
+
+.*: +file format .*arc.*
+
+
+Disassembly of section .text:
+
+[0-9a-f]+ <.text>:
+   0:	2067 0c00           	aex	r0,\[mlx\]
+   4:	216a 0c40           	lr	r1,\[mly\]
+   8:	266b 7c00 0000 0012 	sr	0x12,\[mlx\]
diff --git a/gas/testsuite/gas/arc/textauxregister.s b/gas/testsuite/gas/arc/textauxregister.s
new file mode 100644
index 0000000..8b56ea3
--- /dev/null
+++ b/gas/testsuite/gas/arc/textauxregister.s
@@ -0,0 +1,6 @@
+	.extAuxRegister mlx, 0x30, r|w
+	.extAuxRegister mly, 0x31, r|w
+
+	aex	r0,[mlx]
+	lr	r1,[mly]
+	sr	0x12,[mlx]
diff --git a/gas/testsuite/gas/arc/textcondcode.d b/gas/testsuite/gas/arc/textcondcode.d
new file mode 100644
index 0000000..9671c01
--- /dev/null
+++ b/gas/testsuite/gas/arc/textcondcode.d
@@ -0,0 +1,13 @@
+#objdump: -dr
+
+.*: +file format .*arc.*
+
+
+Disassembly of section .text:
+
+[0-9a-f]+ <.text>:
+   0:	23c0 00ed           	add.hi	r3,r3,0x3
+   4:	24c0 012e           	add.ls	r4,r4,0x4
+   8:	25c0 016f           	add.pnz	r5,r5,0x5
+   c:	26c0 01b2           	add.cctst	r6,r6,0x6
+  10:	27c0 01f3           	add.cstst	r7,r7,0x7
diff --git a/gas/testsuite/gas/arc/textcondcode.s b/gas/testsuite/gas/arc/textcondcode.s
new file mode 100644
index 0000000..d2f292d
--- /dev/null
+++ b/gas/testsuite/gas/arc/textcondcode.s
@@ -0,0 +1,8 @@
+	.extCondCode	cctst, 0x12
+	.extCondCode	cstst, 0x13
+
+	add.hi 		r3,r3,3
+        add.ls 		r4,r4,4
+        add.pnz 	r5,r5,5
+	add.cctst 	r6,r6,6
+	add.cstst 	r7,r7,7
diff --git a/gas/testsuite/gas/arc/textcoreregister.d b/gas/testsuite/gas/arc/textcoreregister.d
new file mode 100644
index 0000000..36f78bb
--- /dev/null
+++ b/gas/testsuite/gas/arc/textcoreregister.d
@@ -0,0 +1,12 @@
+#objdump: -dr
+
+.*: +file format .*arc.*
+
+
+Disassembly of section .text:
+
+[0-9a-f]+ <.text>:
+   0:	2000 00b8           	add	accX,r0,r2
+   4:	2100 00f9           	add	accY,r1,r3
+   8:	2000 70c2           	add	r2,accX,r3
+   c:	2100 7e38           	add	accX,accY,accX
diff --git a/gas/testsuite/gas/arc/textcoreregister.s b/gas/testsuite/gas/arc/textcoreregister.s
new file mode 100644
index 0000000..607edc4
--- /dev/null
+++ b/gas/testsuite/gas/arc/textcoreregister.s
@@ -0,0 +1,7 @@
+	.extCoreRegister accX, 56, r|w, can_shortcut
+	.extCoreRegister accY, 57, r|w, can_shortcut
+
+	add	accX, r0, r2
+	add	accY, r1, r3
+	add	r2, accX, r3
+	add	accX, accY, accX
diff --git a/gas/testsuite/gas/arc/textpseudoop.d b/gas/testsuite/gas/arc/textpseudoop.d
new file mode 100644
index 0000000..e196e95
--- /dev/null
+++ b/gas/testsuite/gas/arc/textpseudoop.d
@@ -0,0 +1,11 @@
+#objdump: -dr
+
+.*: +file format .*arc.*
+
+
+Disassembly of section .text:
+
+[0-9a-f]+ <.text>:
+   0:	39da 7010           	custom0.tst	mlx,mlx,r0
+   4:	392f 701b           	custom1	mlx,r0
+   8:	20aa 0041           	lr	r0,\[aux_test\]
diff --git a/gas/testsuite/gas/arc/textpseudoop.s b/gas/testsuite/gas/arc/textpseudoop.s
new file mode 100644
index 0000000..eb1ce30
--- /dev/null
+++ b/gas/testsuite/gas/arc/textpseudoop.s
@@ -0,0 +1,11 @@
+	.extInstruction custom0, 0x07, 0x1a, SUFFIX_COND|SUFFIX_FLAG, SYNTAX_3OP
+	.extInstruction custom1, 0x07, 0x1b, SUFFIX_FLAG, SYNTAX_2OP
+
+	.extCoreRegister mlx, 57, r|w, can_shortcut
+	.extCondCode tst, 0x10
+	.extAuxRegister aux_test, 0x41, r|w
+
+	custom0.tst	mlx,mlx,r0
+	custom1		mlx,r0
+
+	lr	r0, [aux_test]
diff --git a/include/ChangeLog b/include/ChangeLog
index 87333aa..c7ac36b 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,5 +1,16 @@
 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 
+	* opcode/arc.h (flag_class_t): Update.
+	(ARC_OPCODE_NONE): Define.
+	(ARC_OPCODE_ARCALL): Likewise.
+	(ARC_OPCODE_ARCFPX): Likewise.
+	(ARC_REGISTER_READONLY): Likewise.
+	(ARC_REGISTER_WRITEONLY): Likewise.
+	(ARC_REGISTER_NOSHORT_CUT): Likewise.
+	(arc_aux_reg): Add cpu.
+
+2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
+
 	* opcode/arc.h (arc_num_opcodes): Remove.
 	(ARC_SYNTAX_3OP, ARC_SYNTAX_2OP, ARC_OP1_MUST_BE_IMM)
 	(ARC_OP1_IMM_IMPLIED, ARC_SUFFIX_NONE, ARC_SUFFIX_COND)
diff --git a/include/opcode/arc.h b/include/opcode/arc.h
index a98a2d6..7cd78e4 100644
--- a/include/opcode/arc.h
+++ b/include/opcode/arc.h
@@ -77,15 +77,19 @@ typedef enum
 /* Flags class.  */
 typedef enum
   {
-    F_CLASS_NONE,
+    F_CLASS_NONE = 0,
 
     /* At most one flag from the set of flags can appear in the
        instruction.  */
-    F_CLASS_OPTIONAL,
+    F_CLASS_OPTIONAL = (1 << 0),
 
     /* Exactly one from from the set of flags must appear in the
        instruction.  */
-    F_CLASS_REQUIRED,
+    F_CLASS_REQUIRED = (1 << 1),
+
+    /* The conditional code can be extended over the standard variants
+       via .extCondCode pseudo-op.  */
+    F_CLASS_EXTEND = (1 << 2)
   } flag_class_t;
 
 /* The opcode table is an array of struct arc_opcode.  */
@@ -132,12 +136,18 @@ struct arc_opcode
 extern const struct arc_opcode arc_opcodes[];
 
 /* CPU Availability.  */
+#define ARC_OPCODE_NONE     0x0000
 #define ARC_OPCODE_ARC600   0x0001  /* ARC 600 specific insns.  */
 #define ARC_OPCODE_ARC700   0x0002  /* ARC 700 specific insns.  */
 #define ARC_OPCODE_ARCv2EM  0x0004  /* ARCv2 EM specific insns.  */
 #define ARC_OPCODE_ARCv2HS  0x0008  /* ARCv2 HS specific insns.  */
 #define ARC_OPCODE_NPS400   0x0010  /* NPS400 specific insns.  */
 
+/* CPU combi.  */
+#define ARC_OPCODE_ARCALL  (ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700	\
+			    | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS)
+#define ARC_OPCODE_ARCFPX  (ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM)
+
 /* CPU extensions.  */
 #define ARC_EA       0x0001
 #define ARC_CD       0x0001    /* Mutual exclusive with EA.  */
@@ -406,6 +416,11 @@ struct arc_aux_reg
   /* Register address.  */
   int address;
 
+  /* One bit flags for the opcode.  These are primarily used to
+     indicate specific processors and environments support the
+     instructions.  */
+  unsigned cpu;
+
   /* AUX register subclass.  */
   insn_subclass_t subclass;
 
@@ -503,6 +518,9 @@ extern const unsigned arc_num_relax_opcodes;
 #define ARC_SUFFIX_COND		(1 << 1)
 #define ARC_SUFFIX_FLAG		(1 << 2)
 
+#define ARC_REGISTER_READONLY    (1 << 0)
+#define ARC_REGISTER_WRITEONLY   (1 << 1)
+#define ARC_REGISTER_NOSHORT_CUT (1 << 2)
 
 /* Constants needed to initialize extension instructions.  */
 extern const unsigned char flags_none[MAX_INSN_FLGS + 1];
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index bc59c8f..04b4976 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,19 @@
 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 
+	* arc-dis.c (find_format): Check for extension flags.
+	(print_flags): New function.
+	(print_insn_arc): Update for .extCondCode, .extCoreRegister and
+	.extAuxRegister.
+	* arc-ext.c (arcExtMap_coreRegName): Use
+	LAST_EXTENSION_CORE_REGISTER.
+	(arcExtMap_coreReadWrite): Likewise.
+	(dump_ARC_extmap): Update printing.
+	* arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
+	(arc_aux_regs): Add cpu field.
+	* arc-regs.h: Add cpu field, lower case name aux registers.
+
+2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
+
 	* arc-tbl.h: Add rtsc, sleep with no arguments.
 
 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
diff --git a/opcodes/arc-dis.c b/opcodes/arc-dis.c
index 0a03a0f..eb8bd67 100644
--- a/opcodes/arc-dis.c
+++ b/opcodes/arc-dis.c
@@ -172,12 +172,19 @@ find_format (const struct arc_opcode *arc_table,
 	const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx];
 	const unsigned *flgopridx;
 	int foundA = 0, foundB = 0;
+	unsigned int value;
 
+	/* Check first the extensions.  */
+	if (cl_flags->class & F_CLASS_EXTEND)
+	  {
+	    value = (insn[0] & 0x1F);
+	    if (arcExtMap_condCodeName (value))
+	      continue;
+	  }
 	for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx)
 	  {
 	    const struct arc_flag_operand *flg_operand =
 	      &arc_flag_operands[*flgopridx];
-	    unsigned int value;
 
 	    value = (insn[0] >> flg_operand->shift)
 	      & ((1 << flg_operand->bits) - 1);
@@ -203,6 +210,105 @@ find_format (const struct arc_opcode *arc_table,
   return NULL;
 }
 
+static void
+print_flags (const struct arc_opcode *opcode,
+	     unsigned *insn,
+	     struct disassemble_info *info)
+{
+  const unsigned char *flgidx;
+  unsigned int value;
+
+  /* Now extract and print the flags.  */
+  for (flgidx = opcode->flags; *flgidx; flgidx++)
+    {
+      /* Get a valid flag class.  */
+      const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx];
+      const unsigned *flgopridx;
+
+      /* Check first the extensions.  */
+      if (cl_flags->class & F_CLASS_EXTEND)
+	{
+	  const char *name;
+	  value = (insn[0] & 0x1F);
+
+	  name = arcExtMap_condCodeName (value);
+	  if (name)
+	    {
+	      (*info->fprintf_func) (info->stream, ".%s", name);
+	      continue;
+	    }
+	}
+
+      for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx)
+	{
+	  const struct arc_flag_operand *flg_operand =
+	    &arc_flag_operands[*flgopridx];
+
+	  if (!flg_operand->favail)
+	    continue;
+
+	  value = (insn[0] >> flg_operand->shift)
+	    & ((1 << flg_operand->bits) - 1);
+	  if (value == flg_operand->code)
+	    {
+	       /* FIXME!: print correctly nt/t flag.  */
+	      if (!special_flag_p (opcode->name, flg_operand->name))
+		(*info->fprintf_func) (info->stream, ".");
+	      else if (info->insn_type == dis_dref)
+		{
+		  switch (flg_operand->name[0])
+		    {
+		    case 'b':
+		      info->data_size = 1;
+		      break;
+		    case 'h':
+		    case 'w':
+		      info->data_size = 2;
+		      break;
+		    default:
+		      info->data_size = 4;
+		      break;
+		    }
+		}
+	      (*info->fprintf_func) (info->stream, "%s", flg_operand->name);
+	    }
+
+	  if (flg_operand->name[0] == 'd'
+	      && flg_operand->name[1] == 0)
+	    info->branch_delay_insns = 1;
+	}
+    }
+}
+
+static const char *
+get_auxreg (const struct arc_opcode *opcode,
+	    int value,
+	    unsigned isa_mask)
+{
+  const char *name;
+  unsigned int i;
+  const struct arc_aux_reg *auxr = &arc_aux_regs[0];
+
+  if (opcode->class != AUXREG)
+    return NULL;
+
+  name = arcExtMap_auxRegName (value);
+  if (name)
+    return name;
+
+  for (i = 0; i < arc_num_aux_regs; i++, auxr++)
+    {
+      if (!(auxr->cpu & isa_mask))
+	continue;
+
+      if (auxr->subclass != NONE)
+	return NULL;
+
+      if (auxr->address == value)
+	return auxr->name;
+    }
+  return NULL;
+}
 /* Disassemble ARC instructions.  */
 
 static int
@@ -216,7 +322,6 @@ print_insn_arc (bfd_vma memaddr,
   unsigned insn[2] = { 0, 0 };
   unsigned isa_mask;
   const unsigned char *opidx;
-  const unsigned char *flgidx;
   const struct arc_opcode *opcode;
   const extInstruction_t *einsn;
   bfd_boolean need_comma;
@@ -411,51 +516,7 @@ print_insn_arc (bfd_vma memaddr,
 
   pr_debug ("%s: 0x%08x\n", opcode->name, opcode->opcode);
 
-  /* Now extract and print the flags.  */
-  for (flgidx = opcode->flags; *flgidx; flgidx++)
-    {
-      /* Get a valid flag class.  */
-      const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx];
-      const unsigned *flgopridx;
-
-      for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx)
-	{
-	  const struct arc_flag_operand *flg_operand = &arc_flag_operands[*flgopridx];
-	  unsigned int value;
-
-	  if (!flg_operand->favail)
-	    continue;
-
-	  value = (insn[0] >> flg_operand->shift) & ((1 << flg_operand->bits) - 1);
-	  if (value == flg_operand->code)
-	    {
-	       /* FIXME!: print correctly nt/t flag.  */
-	      if (!special_flag_p (opcode->name, flg_operand->name))
-		(*info->fprintf_func) (info->stream, ".");
-	      else if (info->insn_type == dis_dref)
-		{
-		  switch (flg_operand->name[0])
-		    {
-		    case 'b':
-		      info->data_size = 1;
-		      break;
-		    case 'h':
-		    case 'w':
-		      info->data_size = 2;
-		      break;
-		    default:
-		      info->data_size = 4;
-		      break;
-		    }
-		}
-	      (*info->fprintf_func) (info->stream, "%s", flg_operand->name);
-	    }
-
-	  if (flg_operand->name[0] == 'd'
-	      && flg_operand->name[1] == 0)
-	    info->branch_delay_insns = 1;
-	}
-    }
+  print_flags (opcode, insn, info);
 
   if (opcode->operands[0] != 0)
     (*info->fprintf_func) (info->stream, "\t");
@@ -535,17 +596,33 @@ print_insn_arc (bfd_vma memaddr,
       /* Print the operand as directed by the flags.  */
       if (operand->flags & ARC_OPERAND_IR)
 	{
+	  const char *rname;
+
 	  assert (value >=0 && value < 64);
-	  (*info->fprintf_func) (info->stream, "%s", regnames[value]);
+	  rname = arcExtMap_coreRegName (value);
+	  if (!rname)
+	    rname = regnames[value];
+	  (*info->fprintf_func) (info->stream, "%s", rname);
 	  if (operand->flags & ARC_OPERAND_TRUNCATE)
-	    (*info->fprintf_func) (info->stream, "%s", regnames[value+1]);
+	    {
+	      rname = arcExtMap_coreRegName (value + 1);
+	      if (!rname)
+		rname = regnames[value + 1];
+	      (*info->fprintf_func) (info->stream, "%s", rname);
+	    }
 	}
       else if (operand->flags & ARC_OPERAND_LIMM)
 	{
-	  (*info->fprintf_func) (info->stream, "%#x", insn[1]);
-	  if (info->insn_type == dis_branch
-	      || info->insn_type == dis_jsr)
-	    info->target = (bfd_vma) insn[1];
+	  const char *rname = get_auxreg (opcode, insn[1], isa_mask);
+	  if (rname && open_braket)
+	    (*info->fprintf_func) (info->stream, "%s", rname);
+	  else
+	    {
+	      (*info->fprintf_func) (info->stream, "%#x", insn[1]);
+	      if (info->insn_type == dis_branch
+		  || info->insn_type == dis_jsr)
+		info->target = (bfd_vma) insn[1];
+	    }
 	}
       else if (operand->flags & ARC_OPERAND_PCREL)
 	{
@@ -557,16 +634,30 @@ print_insn_arc (bfd_vma memaddr,
 	  info->target = (bfd_vma) (memaddr & ~3) + value;
 	}
       else if (operand->flags & ARC_OPERAND_SIGNED)
-	(*info->fprintf_func) (info->stream, "%d", value);
+	{
+	  const char *rname = get_auxreg (opcode, value, isa_mask);
+	  if (rname && open_braket)
+	    (*info->fprintf_func) (info->stream, "%s", rname);
+	  else
+	    (*info->fprintf_func) (info->stream, "%d", value);
+	}
       else
-	if (operand->flags & ARC_OPERAND_TRUNCATE
-	    && !(operand->flags & ARC_OPERAND_ALIGNED32)
-	    && !(operand->flags & ARC_OPERAND_ALIGNED16)
-	    && value > 0 && value <= 14)
-	  (*info->fprintf_func) (info->stream, "r13-%s",
-				 regnames[13 + value - 1]);
-	else
-	  (*info->fprintf_func) (info->stream, "%#x", value);
+	{
+	  if (operand->flags & ARC_OPERAND_TRUNCATE
+	      && !(operand->flags & ARC_OPERAND_ALIGNED32)
+	      && !(operand->flags & ARC_OPERAND_ALIGNED16)
+	      && value > 0 && value <= 14)
+	    (*info->fprintf_func) (info->stream, "r13-%s",
+				   regnames[13 + value - 1]);
+	  else
+	    {
+	      const char *rname = get_auxreg (opcode, value, isa_mask);
+	      if (rname && open_braket)
+		(*info->fprintf_func) (info->stream, "%s", rname);
+	      else
+		(*info->fprintf_func) (info->stream, "%#x", value);
+	    }
+	}
 
       need_comma = TRUE;
 
diff --git a/opcodes/arc-ext.c b/opcodes/arc-ext.c
index 45734a0..1d63813 100644
--- a/opcodes/arc-ext.c
+++ b/opcodes/arc-ext.c
@@ -372,7 +372,7 @@ const char *
 arcExtMap_coreRegName (int regnum)
 {
   if (regnum < FIRST_EXTENSION_CORE_REGISTER
-      || regnum > LAST_EXTENSION_CONDITION_CODE)
+      || regnum > LAST_EXTENSION_CORE_REGISTER)
     return NULL;
   return arc_extension_map.
     coreRegisters[regnum - FIRST_EXTENSION_CORE_REGISTER].name;
@@ -384,7 +384,7 @@ enum ExtReadWrite
 arcExtMap_coreReadWrite (int regnum)
 {
   if (regnum < FIRST_EXTENSION_CORE_REGISTER
-      || regnum > LAST_EXTENSION_CONDITION_CODE)
+      || regnum > LAST_EXTENSION_CORE_REGISTER)
     return REG_INVALID;
   return arc_extension_map.
     coreRegisters[regnum - FIRST_EXTENSION_CORE_REGISTER].rw;
@@ -493,8 +493,9 @@ dump_ARC_extmap (void)
 	struct ExtCoreRegister reg = arc_extension_map.coreRegisters[i];
 
 	if (reg.name)
-	    printf ("CORE: %s %d %s\n", reg.name, reg.number,
-		    ExtReadWrite_image (reg.rw));
+	  printf ("CORE: 0x%04x %s %s\n", reg.number,
+		  ExtReadWrite_image (reg.rw),
+		  reg.name);
     }
 
     for (i = 0; i < NUM_EXT_COND; i++)
diff --git a/opcodes/arc-opc.c b/opcodes/arc-opc.c
index 028b80b..5603ded 100644
--- a/opcodes/arc-opc.c
+++ b/opcodes/arc-opc.c
@@ -1048,12 +1048,13 @@ const struct arc_flag_class arc_flag_classes[] =
   { F_CLASS_NONE, { F_NULL } },
 
 #define C_CC	    (C_EMPTY + 1)
-  { F_CLASS_OPTIONAL, { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL,
-			F_NOTZERO, F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS,
-			F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
-			F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW,
-			F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT,
-			F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
+  { F_CLASS_OPTIONAL | F_CLASS_EXTEND,
+    { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL,
+      F_NOTZERO, F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS,
+      F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
+      F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW,
+      F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT,
+      F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
 
 #define C_AA_ADDR3  (C_CC + 1)
 #define C_AA27	    (C_CC + 1)
@@ -1729,8 +1730,8 @@ const unsigned arc_num_pseudo_insn =
 const struct arc_aux_reg arc_aux_regs[] =
 {
 #undef DEF
-#define DEF(ADDR, SUBCLASS, NAME)		\
-  { ADDR, SUBCLASS, #NAME, sizeof (#NAME)-1 },
+#define DEF(ADDR, CPU, SUBCLASS, NAME)		\
+  { ADDR, CPU, SUBCLASS, #NAME, sizeof (#NAME)-1 },
 
 #include "arc-regs.h"
 
diff --git a/opcodes/arc-regs.h b/opcodes/arc-regs.h
index f3f6f87..c0df569 100644
--- a/opcodes/arc-regs.h
+++ b/opcodes/arc-regs.h
@@ -19,366 +19,365 @@
    along with this program; if not, write to the Free Software Foundation,
    Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
 
-DEF (0x0,   NONE, STATUS)
-DEF (0x1,   NONE, SEMAPHORE)
-DEF (0x2,   NONE, LP_START)
-DEF (0x3,   NONE, LP_END)
-DEF (0x4,   NONE, IDENTITY)
-DEF (0x5,   NONE, DEBUG)
-DEF (0x6,   NONE, PC)
-DEF (0x7,   NONE, ADCR)
-DEF (0x8,   NONE, APCR)
-DEF (0x9,   NONE, ACR)
-DEF (0xA,   NONE, STATUS32)
-DEF (0xB,   NONE, STATUS32_L1)
-DEF (0xC,   NONE, STATUS32_L2)
-DEF (0xF,   NONE, BPU_FLUSH)
-DEF (0x10,  NONE, IVIC)
-DEF (0x10,  NONE, IC_IVIC)
-DEF (0x11,  NONE, CHE_MODE)
-DEF (0x11,  NONE, IC_CTRL)
-DEF (0x12,  NONE, MULHI)
-DEF (0x13,  NONE, LOCKLINE)
-DEF (0x13,  NONE, IC_LIL)
-DEF (0x14,  NONE, DMC_CODE_RAM)
-DEF (0x15,  NONE, TAG_ADDR_MASK)
-DEF (0x16,  NONE, TAG_DATA_MASK)
-DEF (0x17,  NONE, LINE_LENGTH_MASK)
-DEF (0x18,  NONE, AUX_LDST_RAM)
-DEF (0x18,  NONE, AUX_DCCM)
-DEF (0x19,  NONE, UNLOCKLINE)
-DEF (0x19,  NONE, IC_IVIL)
-DEF (0x1A,  NONE, IC_RAM_ADDRESS)
-DEF (0x1B,  NONE, IC_TAG)
-DEF (0x1C,  NONE, IC_WP)
-DEF (0x1D,  NONE, IC_DATA)
-DEF (0x20,  NONE, SRAM_SEQ)
-DEF (0x21,  NONE, COUNT0)
-DEF (0x22,  NONE, CONTROL0)
-DEF (0x23,  NONE, LIMIT0)
-DEF (0x24,  NONE, PCPORT)
-DEF (0x25,  NONE, INT_VECTOR_BASE)
-DEF (0x26,  NONE, AUX_VBFDW_MODE)
-DEF (0x26,  NONE, JLI_BASE)
-DEF (0x27,  NONE, AUX_VBFDW_BM0)
-DEF (0x28,  NONE, AUX_VBFDW_BM1)
-DEF (0x29,  NONE, AUX_VBFDW_ACCU)
-DEF (0x2A,  NONE, AUX_VBFDW_OFST)
-DEF (0x2B,  NONE, AUX_VBFDW_INTSTAT)
-DEF (0x2C,  NONE, AUX_XMAC0_24)
-DEF (0x2D,  NONE, AUX_XMAC1_24)
-DEF (0x2E,  NONE, AUX_XMAC2_24)
-DEF (0x2F,  NONE, AUX_FBF_STORE_16)
-DEF (0x30,  NONE, AX0)
-DEF (0x31,  NONE, AX1)
-DEF (0x32,  NONE, AUX_CRC_POLY)
-DEF (0x33,  NONE, AUX_CRC_MODE)
-DEF (0x34,  NONE, MX0)
-DEF (0x35,  NONE, MX1)
-DEF (0x36,  NONE, MY0)
-DEF (0x37,  NONE, MY1)
-DEF (0x38,  NONE, XYCONFIG)
-DEF (0x39,  NONE, SCRATCH_A)
-DEF (0x3A,  NONE, BURSTSYS)
-DEF (0x3A,  NONE, TSCH)
-DEF (0x3B,  NONE, BURSTXYM)
-DEF (0x3C,  NONE, BURSTSZ)
-DEF (0x3D,  NONE, BURSTVAL)
-DEF (0x40,  NONE, XTP_NEWVAL)
-DEF (0x41,  NONE, AUX_MACMODE)
-DEF (0x42,  NONE, LSP_NEWVAL)
-DEF (0x43,  NONE, AUX_IRQ_LV12)
-DEF (0x44,  NONE, AUX_XMAC0)
-DEF (0x45,  NONE, AUX_XMAC1)
-DEF (0x46,  NONE, AUX_XMAC2)
-DEF (0x47,  NONE, DC_IVDC)
-DEF (0x48,  NONE, DC_CTRL)
-DEF (0x49,  NONE, DC_LDL)
-DEF (0x4A,  NONE, DC_IVDL)
-DEF (0x4B,  NONE, DC_FLSH)
-DEF (0x4C,  NONE, DC_FLDL)
-DEF (0x50,  NONE, HEXDATA)
-DEF (0x51,  NONE, HEXCTRL)
-DEF (0x52,  NONE, LED)
-DEF (0x56,  NONE, DILSTAT)
-DEF (0x57,  NONE, SWSTAT)
-DEF (0x58,  NONE, DC_RAM_ADDR)
-DEF (0x59,  NONE, DC_TAG)
-DEF (0x5A,  NONE, DC_WP)
-DEF (0x5B,  NONE, DC_DATA)
-DEF (0x61,  NONE, DCCM_BASE_BUILD)
-DEF (0x62,  NONE, CRC_BUILD)
-DEF (0x63,  NONE, BTA_LINK_BUILD)
-DEF (0x64,  NONE, VBFDW_BUILD)
-DEF (0x65,  NONE, EA_BUILD)
-DEF (0x66,  NONE, DATASPACE)
-DEF (0x67,  NONE, MEMSUBSYS)
-DEF (0x68,  NONE, VECBASE_AC_BUILD)
-DEF (0x69,  NONE, P_BASE_ADDR)
-DEF (0x6A,  NONE, DATA_UNCACHED_BUILD)
-DEF (0x6B,  NONE, FP_BUILD)
-DEF (0x6C,  NONE, DPFP_BUILD)
-DEF (0x6D,  NONE, MPU_BUILD)
-DEF (0x6E,  NONE, RF_BUILD)
-DEF (0x6F,  NONE, MMU_BUILD)
-DEF (0x70,  NONE, AA2_BUILD)
-DEF (0x71,  NONE, VECBASE_BUILD)
-DEF (0x72,  NONE, D_CACHE_BUILD)
-DEF (0x73,  NONE, MADI_BUILD)
-DEF (0x74,  NONE, DCCM_BUILD)
-DEF (0x75,  NONE, TIMER_BUILD)
-DEF (0x76,  NONE, AP_BUILD)
-DEF (0x77,  NONE, I_CACHE_BUILD)
-DEF (0x78,  NONE, ICCM_BUILD)
-DEF (0x79,  NONE, DSPRAM_BUILD)
-DEF (0x7A,  NONE, MAC_BUILD)
-DEF (0x7B,  NONE, MULTIPLY_BUILD)
-DEF (0x7C,  NONE, SWAP_BUILD)
-DEF (0x7D,  NONE, NORM_BUILD)
-DEF (0x7E,  NONE, MINMAX_BUILD)
-DEF (0x7F,  NONE, BARREL_BUILD)
-DEF (0x80,  NONE, AX0)
-DEF (0x81,  NONE, AX1)
-DEF (0x82,  NONE, AX2)
-DEF (0x83,  NONE, AX3)
-DEF (0x84,  NONE, AY0)
-DEF (0x85,  NONE, AY1)
-DEF (0x86,  NONE, AY2)
-DEF (0x87,  NONE, AY3)
-DEF (0x88,  NONE, MX00)
-DEF (0x89,  NONE, MX01)
-DEF (0x8A,  NONE, MX10)
-DEF (0x8B,  NONE, MX11)
-DEF (0x8C,  NONE, MX20)
-DEF (0x8D,  NONE, MX21)
-DEF (0x8E,  NONE, MX30)
-DEF (0x8F,  NONE, MX31)
-DEF (0x90,  NONE, MY00)
-DEF (0x91,  NONE, MY01)
-DEF (0x92,  NONE, MY10)
-DEF (0x93,  NONE, MY11)
-DEF (0x94,  NONE, MY20)
-DEF (0x95,  NONE, MY21)
-DEF (0x96,  NONE, MY30)
-DEF (0x97,  NONE, MY31)
-DEF (0x98,  NONE, XYCONFIG)
-DEF (0x99,  NONE, BURSTSYS)
-DEF (0x9A,  NONE, BURSTXYM)
-DEF (0x9B,  NONE, BURSTSZ)
-DEF (0x9C,  NONE, BURSTVAL)
-DEF (0x9D,  NONE, XYLSBASEX)
-DEF (0x9E,  NONE, XYLSBASEY)
-DEF (0x9F,  NONE, AUX_XMACLW_H)
-DEF (0xA0,  NONE, AUX_XMACLW_L)
-DEF (0xA1,  NONE, SE_CTRL)
-DEF (0xA2,  NONE, SE_STAT)
-DEF (0xA3,  NONE, SE_ERR)
-DEF (0xA4,  NONE, SE_EADR)
-DEF (0xA5,  NONE, SE_SPC)
-DEF (0xA6,  NONE, SDM_BASE)
-DEF (0xA7,  NONE, SCM_BASE)
-DEF (0xA8,  NONE, SE_DBG_CTRL)
-DEF (0xA9,  NONE, SE_DBG_DATA0)
-DEF (0xAA,  NONE, SE_DBG_DATA1)
-DEF (0xAB,  NONE, SE_DBG_DATA2)
-DEF (0xAC,  NONE, SE_DBG_DATA3)
-DEF (0xAD,  NONE, SE_WATCH)
-DEF (0xC0,  NONE, BPU_BUILD)
-DEF (0xC1,  NONE, ARC600_BUILD_CONFIG)
-DEF (0xC2,  NONE, ISA_CONFIG)
-DEF (0xF4,  NONE, HWP_BUILD)
-DEF (0xF5,  NONE, PCT_BUILD)
-DEF (0xF6,  NONE, CC_BUILD)
-DEF (0xF7,  NONE, PM_BCR)
-DEF (0xF8,  NONE, SCQ_SWITCH_BUILD)
-DEF (0xF9,  NONE, VRAPTOR_BUILD)
-DEF (0xFA,  NONE, DMA_CONFIG)
-DEF (0xFB,  NONE, SIMD_CONFIG)
-DEF (0xFC,  NONE, VLC_BUILD)
-DEF (0xFD,  NONE, SIMD_DMA_BUILD)
-DEF (0xFE,  NONE, IFETCH_QUEUE_BUILD)
-DEF (0xFF,  NONE, SMART_BUILD)
-DEF (0x100, NONE, COUNT1)
-DEF (0x101, NONE, CONTROL1)
-DEF (0x102, NONE, LIMIT1)
-DEF (0x103, NONE, TIMER_XX)
-DEF (0x120, NONE, ARCANGEL_PERIPH_XX)
-DEF (0x140, NONE, PERIPH_XX)
-DEF (0x200, NONE, AUX_IRQ_LEV)
-DEF (0x201, NONE, AUX_IRQ_HINT)
-DEF (0x202, NONE, AUX_INTER_CORE_INTERRUPT)
-DEF (0x210, NONE, AES_AUX_0)
-DEF (0x211, NONE, AES_AUX_1)
-DEF (0x212, NONE, AES_AUX_2)
-DEF (0x213, NONE, AES_CRYPT_MODE)
-DEF (0x214, NONE, AES_AUXS)
-DEF (0x215, NONE, AES_AUXI)
-DEF (0x216, NONE, AES_AUX_3)
-DEF (0x217, NONE, AES_AUX_4)
-DEF (0x218, NONE, ARITH_CTL_AUX)
-DEF (0x219, NONE, DES_AUX)
-DEF (0x220, NONE, AP_AMV0)
-DEF (0x221, NONE, AP_AMM0)
-DEF (0x222, NONE, AP_AC0)
-DEF (0x223, NONE, AP_AMV1)
-DEF (0x224, NONE, AP_AMM1)
-DEF (0x225, NONE, AP_AC1)
-DEF (0x226, NONE, AP_AMV2)
-DEF (0x227, NONE, AP_AMM2)
-DEF (0x228, NONE, AP_AC2)
-DEF (0x229, NONE, AP_AMV3)
-DEF (0x22A, NONE, AP_AMM3)
-DEF (0x22B, NONE, AP_AC3)
-DEF (0x22C, NONE, AP_AMV4)
-DEF (0x22D, NONE, AP_AMM4)
-DEF (0x22E, NONE, AP_AC4)
-DEF (0x22F, NONE, AP_AMV5)
-DEF (0x230, NONE, AP_AMM5)
-DEF (0x231, NONE, AP_AC5)
-DEF (0x232, NONE, AP_AMV6)
-DEF (0x233, NONE, AP_AMM6)
-DEF (0x234, NONE, AP_AC6)
-DEF (0x235, NONE, AP_AMV7)
-DEF (0x236, NONE, AP_AMM7)
-DEF (0x237, NONE, AP_AC7)
-DEF (0x278, NONE, PCT_CONTROL)
-DEF (0x279, NONE, PCT_BANK)
-DEF (0x300, DPX,  FP_STATUS)
-DEF (0x301, DPX,  AUX_DPFP1L)
-DEF (0x301, DPX,  D1L)
-DEF (0x302, DPX,  AUX_DPFP1H)
-DEF (0x302, DPX,  D1H)
-DEF (0x302, DPA,  D1L)
-DEF (0x303, DPX,  AUX_DPFP2L)
-DEF (0x303, DPX,  D2L)
-DEF (0x303, DPA,  D1H)
-DEF (0x304, DPX,  AUX_DPFP2H)
-DEF (0x304, DPX,  D2H)
-DEF (0x304, DPA,  D2L)
-DEF (0x305, DPX,  DPFP_STATUS)
-DEF (0x305, DPA,  D2H)
-DEF (0x306, NONE, RTT)
-DEF (0x400, NONE, ERET)
-DEF (0x401, NONE, ERBTA)
-DEF (0x402, NONE, ERSTATUS)
-DEF (0x403, NONE, ECR)
-DEF (0x404, NONE, EFA)
-DEF (0x405, NONE, TLBPD0)
-DEF (0x406, NONE, TLBPD1)
-DEF (0x407, NONE, TLBIndex)
-DEF (0x408, NONE, TLBCommand)
-DEF (0x409, NONE, PID)
-DEF (0x409, NONE, MPUEN)
-DEF (0x40A, NONE, ICAUSE1)
-DEF (0x40B, NONE, ICAUSE2)
-DEF (0x40C, NONE, AUX_IENABLE)
-DEF (0x40D, NONE, AUX_ITRIGGER)
-DEF (0x410, NONE, XPU)
-DEF (0x412, NONE, BTA)
-DEF (0x413, NONE, BTA_L1)
-DEF (0x414, NONE, BTA_L2)
-DEF (0x415, NONE, AUX_IRQ_PULSE_CANCEL)
-DEF (0x416, NONE, AUX_IRQ_PENDING)
-DEF (0x418, NONE, SCRATCH_DATA0)
-DEF (0x420, NONE, MPUIC)
-DEF (0x421, NONE, MPUFA)
-DEF (0x422, NONE, MPURDB0)
-DEF (0x423, NONE, MPURDP0)
-DEF (0x424, NONE, MPURDB1)
-DEF (0x425, NONE, MPURDP1)
-DEF (0x426, NONE, MPURDB2)
-DEF (0x427, NONE, MPURDP2)
-DEF (0x428, NONE, MPURDB3)
-DEF (0x429, NONE, MPURDP3)
-DEF (0x42A, NONE, MPURDB4)
-DEF (0x42B, NONE, MPURDP4)
-DEF (0x42C, NONE, MPURDB5)
-DEF (0x42D, NONE, MPURDP5)
-DEF (0x42E, NONE, MPURDB6)
-DEF (0x42F, NONE, MPURDP6)
-DEF (0x430, NONE, MPURDB7)
-DEF (0x431, NONE, MPURDP7)
-DEF (0x432, NONE, MPURDB8)
-DEF (0x433, NONE, MPURDP8)
-DEF (0x434, NONE, MPURDB9)
-DEF (0x435, NONE, MPURDP9)
-DEF (0x436, NONE, MPURDB10)
-DEF (0x437, NONE, MPURDP10)
-DEF (0x438, NONE, MPURDB11)
-DEF (0x439, NONE, MPURDP11)
-DEF (0x43A, NONE, MPURDB12)
-DEF (0x43B, NONE, MPURDP12)
-DEF (0x43C, NONE, MPURDB13)
-DEF (0x43D, NONE, MPURDP13)
-DEF (0x43E, NONE, MPURDB14)
-DEF (0x43F, NONE, MPURDP14)
-DEF (0x440, NONE, MPURDB15)
-DEF (0x441, NONE, MPURDP15)
-DEF (0x44F, NONE, EIA_FLAGS)
-DEF (0x450, NONE, PM_STATUS)
-DEF (0x451, NONE, WAKE)
-DEF (0x452, NONE, DVFS_PERFORMANCE)
-DEF (0x453, NONE, PWR_CTRL)
-DEF (0x500, NONE, AUX_VLC_BUF_IDX)
-DEF (0x501, NONE, AUX_VLC_READ_BUF)
-DEF (0x502, NONE, AUX_VLC_VALID_BITS)
-DEF (0x503, NONE, AUX_VLC_BUF_IN)
-DEF (0x504, NONE, AUX_VLC_BUF_FREE)
-DEF (0x505, NONE, AUX_VLC_IBUF_STATUS)
-DEF (0x506, NONE, AUX_VLC_SETUP)
-DEF (0x507, NONE, AUX_VLC_BITS)
-DEF (0x508, NONE, AUX_VLC_TABLE)
-DEF (0x509, NONE, AUX_VLC_GET_SYMBOL)
-DEF (0x50A, NONE, AUX_VLC_READ_SYMBOL)
-DEF (0x510, NONE, AUX_UCAVLC_SETUP)
-DEF (0x511, NONE, AUX_UCAVLC_STATE)
-DEF (0x512, NONE, AUX_CAVLC_ZERO_LEFT)
-DEF (0x514, NONE, AUX_UVLC_I_STATE)
-DEF (0x51C, NONE, AUX_VLC_DMA_PTR)
-DEF (0x51D, NONE, AUX_VLC_DMA_END)
-DEF (0x51E, NONE, AUX_VLC_DMA_ESC)
-DEF (0x51F, NONE, AUX_VLC_DMA_CTRL)
-DEF (0x520, NONE, AUX_VLC_GET_0BIT)
-DEF (0x521, NONE, AUX_VLC_GET_1BIT)
-DEF (0x522, NONE, AUX_VLC_GET_2BIT)
-DEF (0x523, NONE, AUX_VLC_GET_3BIT)
-DEF (0x524, NONE, AUX_VLC_GET_4BIT)
-DEF (0x525, NONE, AUX_VLC_GET_5BIT)
-DEF (0x526, NONE, AUX_VLC_GET_6BIT)
-DEF (0x527, NONE, AUX_VLC_GET_7BIT)
-DEF (0x528, NONE, AUX_VLC_GET_8BIT)
-DEF (0x529, NONE, AUX_VLC_GET_9BIT)
-DEF (0x52A, NONE, AUX_VLC_GET_10BIT)
-DEF (0x52B, NONE, AUX_VLC_GET_11BIT)
-DEF (0x52C, NONE, AUX_VLC_GET_12BIT)
-DEF (0x52D, NONE, AUX_VLC_GET_13BIT)
-DEF (0x52E, NONE, AUX_VLC_GET_14BIT)
-DEF (0x52F, NONE, AUX_VLC_GET_15BIT)
-DEF (0x530, NONE, AUX_VLC_GET_16BIT)
-DEF (0x531, NONE, AUX_VLC_GET_17BIT)
-DEF (0x532, NONE, AUX_VLC_GET_18BIT)
-DEF (0x533, NONE, AUX_VLC_GET_19BIT)
-DEF (0x534, NONE, AUX_VLC_GET_20BIT)
-DEF (0x535, NONE, AUX_VLC_GET_21BIT)
-DEF (0x536, NONE, AUX_VLC_GET_22BIT)
-DEF (0x537, NONE, AUX_VLC_GET_23BIT)
-DEF (0x538, NONE, AUX_VLC_GET_24BIT)
-DEF (0x539, NONE, AUX_VLC_GET_25BIT)
-DEF (0x53A, NONE, AUX_VLC_GET_26BIT)
-DEF (0x53B, NONE, AUX_VLC_GET_27BIT)
-DEF (0x53C, NONE, AUX_VLC_GET_28BIT)
-DEF (0x53D, NONE, AUX_VLC_GET_29BIT)
-DEF (0x53E, NONE, AUX_VLC_GET_30BIT)
-DEF (0x53F, NONE, AUX_VLC_GET_31BIT)
-DEF (0x540, NONE, AUX_CABAC_CTRL)
-DEF (0x541, NONE, AUX_CABAC_CTX_STATE)
-DEF (0x542, NONE, AUX_CABAC_COD_PARAM)
-DEF (0x543, NONE, AUX_CABAC_MISC0)
-DEF (0x544, NONE, AUX_CABAC_MISC1)
-DEF (0x545, NONE, AUX_CABAC_MISC2)
-DEF (0x600, NONE, ARC600_BUILD_CONFIG)
-DEF (0x700, NONE, SMART_CONTROL)
-DEF (0x701, NONE, SMART_DATA_0)
-DEF (0x701, NONE, SMART_DATA_1)
-DEF (0x701, NONE, SMART_DATA_2)
-DEF (0x701, NONE, SMART_DATA_3)
+DEF (0x0,   ARC_OPCODE_ARCALL, NONE, status)
+DEF (0x1,   ARC_OPCODE_ARCALL, NONE, semaphore)
+DEF (0x2,   ARC_OPCODE_ARCALL, NONE, lp_start)
+DEF (0x3,   ARC_OPCODE_ARCALL, NONE, lp_end)
+DEF (0x4,   ARC_OPCODE_ARCALL, NONE, identity)
+DEF (0x5,   ARC_OPCODE_ARCALL, NONE, debug)
+DEF (0x6,   ARC_OPCODE_ARCALL, NONE, pc)
+DEF (0x7,   ARC_OPCODE_ARCALL, NONE, adcr)
+DEF (0x8,   ARC_OPCODE_ARCALL, NONE, apcr)
+DEF (0x9,   ARC_OPCODE_ARCALL, NONE, acr)
+DEF (0xa,   ARC_OPCODE_ARCALL, NONE, status32)
+DEF (0xb,   ARC_OPCODE_ARCALL, NONE, status32_l1)
+DEF (0xc,   ARC_OPCODE_ARCALL, NONE, status32_l2)
+DEF (0xf,   ARC_OPCODE_ARCALL, NONE, bpu_flush)
+DEF (0x10,  ARC_OPCODE_ARCALL, NONE, ivic)
+DEF (0x10,  ARC_OPCODE_ARCALL, NONE, ic_ivic)
+DEF (0x11,  ARC_OPCODE_ARCALL, NONE, che_mode)
+DEF (0x11,  ARC_OPCODE_ARCALL, NONE, ic_ctrl)
+DEF (0x12,  ARC_OPCODE_ARCALL, NONE, mulhi)
+DEF (0x13,  ARC_OPCODE_ARCALL, NONE, lockline)
+DEF (0x13,  ARC_OPCODE_ARCALL, NONE, ic_lil)
+DEF (0x14,  ARC_OPCODE_ARCALL, NONE, dmc_code_ram)
+DEF (0x15,  ARC_OPCODE_ARCALL, NONE, tag_addr_mask)
+DEF (0x16,  ARC_OPCODE_ARCALL, NONE, tag_data_mask)
+DEF (0x17,  ARC_OPCODE_ARCALL, NONE, line_length_mask)
+DEF (0x18,  ARC_OPCODE_ARCALL, NONE, aux_ldst_ram)
+DEF (0x18,  ARC_OPCODE_ARCALL, NONE, aux_dccm)
+DEF (0x19,  ARC_OPCODE_ARCALL, NONE, unlockline)
+DEF (0x19,  ARC_OPCODE_ARCALL, NONE, ic_ivil)
+DEF (0x1a,  ARC_OPCODE_ARCALL, NONE, ic_ram_address)
+DEF (0x1b,  ARC_OPCODE_ARCALL, NONE, ic_tag)
+DEF (0x1c,  ARC_OPCODE_ARCALL, NONE, ic_wp)
+DEF (0x1d,  ARC_OPCODE_ARCALL, NONE, ic_data)
+DEF (0x20,  ARC_OPCODE_ARCALL, NONE, sram_seq)
+DEF (0x21,  ARC_OPCODE_ARCALL, NONE, count0)
+DEF (0x22,  ARC_OPCODE_ARCALL, NONE, control0)
+DEF (0x23,  ARC_OPCODE_ARCALL, NONE, limit0)
+DEF (0x24,  ARC_OPCODE_ARCALL, NONE, pcport)
+DEF (0x25,  ARC_OPCODE_ARCALL, NONE, int_vector_base)
+DEF (0x26,  ARC_OPCODE_ARCALL, NONE, aux_vbfdw_mode)
+DEF (0x26,  ARC_OPCODE_ARCALL, NONE, jli_base)
+DEF (0x27,  ARC_OPCODE_ARCALL, NONE, aux_vbfdw_bm0)
+DEF (0x28,  ARC_OPCODE_ARCALL, NONE, aux_vbfdw_bm1)
+DEF (0x29,  ARC_OPCODE_ARCALL, NONE, aux_vbfdw_accu)
+DEF (0x2a,  ARC_OPCODE_ARCALL, NONE, aux_vbfdw_ofst)
+DEF (0x2b,  ARC_OPCODE_ARCALL, NONE, aux_vbfdw_intstat)
+DEF (0x2c,  ARC_OPCODE_ARCALL, NONE, aux_xmac0_24)
+DEF (0x2d,  ARC_OPCODE_ARCALL, NONE, aux_xmac1_24)
+DEF (0x2e,  ARC_OPCODE_ARCALL, NONE, aux_xmac2_24)
+DEF (0x2f,  ARC_OPCODE_ARCALL, NONE, aux_fbf_store_16)
+DEF (0x30,  ARC_OPCODE_NONE,   NONE, ax0)
+DEF (0x31,  ARC_OPCODE_NONE,   NONE, ax1)
+DEF (0x32,  ARC_OPCODE_NONE,   NONE, aux_crc_poly)
+DEF (0x33,  ARC_OPCODE_NONE,   NONE, aux_crc_mode)
+DEF (0x34,  ARC_OPCODE_NONE,   NONE, mx0)
+DEF (0x35,  ARC_OPCODE_NONE,   NONE, mx1)
+DEF (0x36,  ARC_OPCODE_NONE,   NONE, my0)
+DEF (0x37,  ARC_OPCODE_NONE,   NONE, my1)
+DEF (0x38,  ARC_OPCODE_NONE,   NONE, xyconfig)
+DEF (0x39,  ARC_OPCODE_NONE,   NONE, scratch_a)
+DEF (0x3a,  ARC_OPCODE_NONE,   NONE, burstsys)
+DEF (0x3a,  ARC_OPCODE_NONE,   NONE, tsch)
+DEF (0x3b,  ARC_OPCODE_NONE,   NONE, burstxym)
+DEF (0x3c,  ARC_OPCODE_NONE,   NONE, burstsz)
+DEF (0x3d,  ARC_OPCODE_NONE,   NONE, burstval)
+DEF (0x40,  ARC_OPCODE_ARCALL, NONE, xtp_newval)
+DEF (0x41,  ARC_OPCODE_ARCALL, NONE, aux_macmode)
+DEF (0x42,  ARC_OPCODE_ARCALL, NONE, lsp_newval)
+DEF (0x43,  ARC_OPCODE_ARCALL, NONE, aux_irq_lv12)
+DEF (0x44,  ARC_OPCODE_ARCALL, NONE, aux_xmac0)
+DEF (0x45,  ARC_OPCODE_ARCALL, NONE, aux_xmac1)
+DEF (0x46,  ARC_OPCODE_ARCALL, NONE, aux_xmac2)
+DEF (0x47,  ARC_OPCODE_ARCALL, NONE, dc_ivdc)
+DEF (0x48,  ARC_OPCODE_ARCALL, NONE, dc_ctrl)
+DEF (0x49,  ARC_OPCODE_ARCALL, NONE, dc_ldl)
+DEF (0x4a,  ARC_OPCODE_ARCALL, NONE, dc_ivdl)
+DEF (0x4b,  ARC_OPCODE_ARCALL, NONE, dc_flsh)
+DEF (0x4c,  ARC_OPCODE_ARCALL, NONE, dc_fldl)
+DEF (0x50,  ARC_OPCODE_ARCALL, NONE, hexdata)
+DEF (0x51,  ARC_OPCODE_ARCALL, NONE, hexctrl)
+DEF (0x52,  ARC_OPCODE_ARCALL, NONE, led)
+DEF (0x56,  ARC_OPCODE_ARCALL, NONE, dilstat)
+DEF (0x57,  ARC_OPCODE_ARCALL, NONE, swstat)
+DEF (0x58,  ARC_OPCODE_ARCALL, NONE, dc_ram_addr)
+DEF (0x59,  ARC_OPCODE_ARCALL, NONE, dc_tag)
+DEF (0x5a,  ARC_OPCODE_ARCALL, NONE, dc_wp)
+DEF (0x5b,  ARC_OPCODE_ARCALL, NONE, dc_data)
+DEF (0x61,  ARC_OPCODE_ARCALL, NONE, dccm_base_build)
+DEF (0x62,  ARC_OPCODE_ARCALL, NONE, crc_build)
+DEF (0x63,  ARC_OPCODE_ARCALL, NONE, bta_link_build)
+DEF (0x64,  ARC_OPCODE_ARCALL, NONE, vbfdw_build)
+DEF (0x65,  ARC_OPCODE_ARCALL, NONE, ea_build)
+DEF (0x66,  ARC_OPCODE_ARCALL, NONE, dataspace)
+DEF (0x67,  ARC_OPCODE_ARCALL, NONE, memsubsys)
+DEF (0x68,  ARC_OPCODE_ARCALL, NONE, vecbase_ac_build)
+DEF (0x69,  ARC_OPCODE_ARCALL, NONE, p_base_addr)
+DEF (0x6a,  ARC_OPCODE_ARCALL, NONE, data_uncached_build)
+DEF (0x6b,  ARC_OPCODE_ARCALL, NONE, fp_build)
+DEF (0x6c,  ARC_OPCODE_ARCALL, NONE, dpfp_build)
+DEF (0x6d,  ARC_OPCODE_ARCALL, NONE, mpu_build)
+DEF (0x6e,  ARC_OPCODE_ARCALL, NONE, rf_build)
+DEF (0x6f,  ARC_OPCODE_ARCALL, NONE, mmu_build)
+DEF (0x70,  ARC_OPCODE_ARCALL, NONE, aa2_build)
+DEF (0x71,  ARC_OPCODE_ARCALL, NONE, vecbase_build)
+DEF (0x72,  ARC_OPCODE_ARCALL, NONE, d_cache_build)
+DEF (0x73,  ARC_OPCODE_ARCALL, NONE, madi_build)
+DEF (0x74,  ARC_OPCODE_ARCALL, NONE, dccm_build)
+DEF (0x75,  ARC_OPCODE_ARCALL, NONE, timer_build)
+DEF (0x76,  ARC_OPCODE_ARCALL, NONE, ap_build)
+DEF (0x77,  ARC_OPCODE_ARCALL, NONE, i_cache_build)
+DEF (0x78,  ARC_OPCODE_ARCALL, NONE, iccm_build)
+DEF (0x79,  ARC_OPCODE_ARCALL, NONE, dspram_build)
+DEF (0x7a,  ARC_OPCODE_ARCALL, NONE, mac_build)
+DEF (0x7b,  ARC_OPCODE_ARCALL, NONE, multiply_build)
+DEF (0x7c,  ARC_OPCODE_ARCALL, NONE, swap_build)
+DEF (0x7d,  ARC_OPCODE_ARCALL, NONE, norm_build)
+DEF (0x7e,  ARC_OPCODE_ARCALL, NONE, minmax_build)
+DEF (0x7f,  ARC_OPCODE_ARCALL, NONE, barrel_build)
+DEF (0x80,  ARC_OPCODE_ARCALL, NONE, ax0)
+DEF (0x81,  ARC_OPCODE_ARCALL, NONE, ax1)
+DEF (0x82,  ARC_OPCODE_ARCALL, NONE, ax2)
+DEF (0x83,  ARC_OPCODE_ARCALL, NONE, ax3)
+DEF (0x84,  ARC_OPCODE_ARCALL, NONE, ay0)
+DEF (0x85,  ARC_OPCODE_ARCALL, NONE, ay1)
+DEF (0x86,  ARC_OPCODE_ARCALL, NONE, ay2)
+DEF (0x87,  ARC_OPCODE_ARCALL, NONE, ay3)
+DEF (0x88,  ARC_OPCODE_ARCALL, NONE, mx00)
+DEF (0x89,  ARC_OPCODE_ARCALL, NONE, mx01)
+DEF (0x8a,  ARC_OPCODE_ARCALL, NONE, mx10)
+DEF (0x8b,  ARC_OPCODE_ARCALL, NONE, mx11)
+DEF (0x8c,  ARC_OPCODE_ARCALL, NONE, mx20)
+DEF (0x8d,  ARC_OPCODE_ARCALL, NONE, mx21)
+DEF (0x8e,  ARC_OPCODE_ARCALL, NONE, mx30)
+DEF (0x8f,  ARC_OPCODE_ARCALL, NONE, mx31)
+DEF (0x90,  ARC_OPCODE_ARCALL, NONE, my00)
+DEF (0x91,  ARC_OPCODE_ARCALL, NONE, my01)
+DEF (0x92,  ARC_OPCODE_ARCALL, NONE, my10)
+DEF (0x93,  ARC_OPCODE_ARCALL, NONE, my11)
+DEF (0x94,  ARC_OPCODE_ARCALL, NONE, my20)
+DEF (0x95,  ARC_OPCODE_ARCALL, NONE, my21)
+DEF (0x96,  ARC_OPCODE_ARCALL, NONE, my30)
+DEF (0x97,  ARC_OPCODE_ARCALL, NONE, my31)
+DEF (0x98,  ARC_OPCODE_ARCALL, NONE, xyconfig)
+DEF (0x99,  ARC_OPCODE_ARCALL, NONE, burstsys)
+DEF (0x9a,  ARC_OPCODE_ARCALL, NONE, burstxym)
+DEF (0x9b,  ARC_OPCODE_ARCALL, NONE, burstsz)
+DEF (0x9c,  ARC_OPCODE_ARCALL, NONE, burstval)
+DEF (0x9d,  ARC_OPCODE_ARCALL, NONE, xylsbasex)
+DEF (0x9e,  ARC_OPCODE_ARCALL, NONE, xylsbasey)
+DEF (0x9f,  ARC_OPCODE_ARCALL, NONE, aux_xmaclw_h)
+DEF (0xa0,  ARC_OPCODE_ARCALL, NONE, aux_xmaclw_l)
+DEF (0xa1,  ARC_OPCODE_ARCALL, NONE, se_ctrl)
+DEF (0xa2,  ARC_OPCODE_ARCALL, NONE, se_stat)
+DEF (0xa3,  ARC_OPCODE_ARCALL, NONE, se_err)
+DEF (0xa4,  ARC_OPCODE_ARCALL, NONE, se_eadr)
+DEF (0xa5,  ARC_OPCODE_ARCALL, NONE, se_spc)
+DEF (0xa6,  ARC_OPCODE_ARCALL, NONE, sdm_base)
+DEF (0xa7,  ARC_OPCODE_ARCALL, NONE, scm_base)
+DEF (0xa8,  ARC_OPCODE_ARCALL, NONE, se_dbg_ctrl)
+DEF (0xa9,  ARC_OPCODE_ARCALL, NONE, se_dbg_data0)
+DEF (0xaa,  ARC_OPCODE_ARCALL, NONE, se_dbg_data1)
+DEF (0xab,  ARC_OPCODE_ARCALL, NONE, se_dbg_data2)
+DEF (0xac,  ARC_OPCODE_ARCALL, NONE, se_dbg_data3)
+DEF (0xad,  ARC_OPCODE_ARCALL, NONE, se_watch)
+DEF (0xc0,  ARC_OPCODE_ARCALL, NONE, bpu_build)
+DEF (0xc1,  ARC_OPCODE_ARC600, NONE, arc600_build_config)
+DEF (0xc2,  ARC_OPCODE_ARCALL, NONE, isa_config)
+DEF (0xf4,  ARC_OPCODE_ARCALL, NONE, hwp_build)
+DEF (0xf5,  ARC_OPCODE_ARCALL, NONE, pct_build)
+DEF (0xf6,  ARC_OPCODE_ARCALL, NONE, cc_build)
+DEF (0xf7,  ARC_OPCODE_ARCALL, NONE, pm_bcr)
+DEF (0xf8,  ARC_OPCODE_ARCALL, NONE, scq_switch_build)
+DEF (0xf9,  ARC_OPCODE_ARCALL, NONE, vraptor_build)
+DEF (0xfa,  ARC_OPCODE_ARCALL, NONE, dma_config)
+DEF (0xfb,  ARC_OPCODE_ARCALL, NONE, simd_config)
+DEF (0xfc,  ARC_OPCODE_ARCALL, NONE, vlc_build)
+DEF (0xfd,  ARC_OPCODE_ARCALL, NONE, simd_dma_build)
+DEF (0xfe,  ARC_OPCODE_ARCALL, NONE, ifetch_queue_build)
+DEF (0xff,  ARC_OPCODE_ARCALL, NONE, smart_build)
+DEF (0x100, ARC_OPCODE_ARCALL, NONE, count1)
+DEF (0x101, ARC_OPCODE_ARCALL, NONE, control1)
+DEF (0x102, ARC_OPCODE_ARCALL, NONE, limit1)
+DEF (0x103, ARC_OPCODE_ARCALL, NONE, timer_xx)
+DEF (0x120, ARC_OPCODE_ARCALL, NONE, arcangel_periph_xx)
+DEF (0x140, ARC_OPCODE_ARCALL, NONE, periph_xx)
+DEF (0x200, ARC_OPCODE_ARCALL, NONE, aux_irq_lev)
+DEF (0x201, ARC_OPCODE_ARCALL, NONE, aux_irq_hint)
+DEF (0x202, ARC_OPCODE_ARCALL, NONE, aux_inter_core_interrupt)
+DEF (0x210, ARC_OPCODE_ARCALL, NONE, aes_aux_0)
+DEF (0x211, ARC_OPCODE_ARCALL, NONE, aes_aux_1)
+DEF (0x212, ARC_OPCODE_ARCALL, NONE, aes_aux_2)
+DEF (0x213, ARC_OPCODE_ARCALL, NONE, aes_crypt_mode)
+DEF (0x214, ARC_OPCODE_ARCALL, NONE, aes_auxs)
+DEF (0x215, ARC_OPCODE_ARCALL, NONE, aes_auxi)
+DEF (0x216, ARC_OPCODE_ARCALL, NONE, aes_aux_3)
+DEF (0x217, ARC_OPCODE_ARCALL, NONE, aes_aux_4)
+DEF (0x218, ARC_OPCODE_ARCALL, NONE, arith_ctl_aux)
+DEF (0x219, ARC_OPCODE_ARCALL, NONE, des_aux)
+DEF (0x220, ARC_OPCODE_ARCALL, NONE, ap_amv0)
+DEF (0x221, ARC_OPCODE_ARCALL, NONE, ap_amm0)
+DEF (0x222, ARC_OPCODE_ARCALL, NONE, ap_ac0)
+DEF (0x223, ARC_OPCODE_ARCALL, NONE, ap_amv1)
+DEF (0x224, ARC_OPCODE_ARCALL, NONE, ap_amm1)
+DEF (0x225, ARC_OPCODE_ARCALL, NONE, ap_ac1)
+DEF (0x226, ARC_OPCODE_ARCALL, NONE, ap_amv2)
+DEF (0x227, ARC_OPCODE_ARCALL, NONE, ap_amm2)
+DEF (0x228, ARC_OPCODE_ARCALL, NONE, ap_ac2)
+DEF (0x229, ARC_OPCODE_ARCALL, NONE, ap_amv3)
+DEF (0x22a, ARC_OPCODE_ARCALL, NONE, ap_amm3)
+DEF (0x22b, ARC_OPCODE_ARCALL, NONE, ap_ac3)
+DEF (0x22c, ARC_OPCODE_ARCALL, NONE, ap_amv4)
+DEF (0x22d, ARC_OPCODE_ARCALL, NONE, ap_amm4)
+DEF (0x22e, ARC_OPCODE_ARCALL, NONE, ap_ac4)
+DEF (0x22f, ARC_OPCODE_ARCALL, NONE, ap_amv5)
+DEF (0x230, ARC_OPCODE_ARCALL, NONE, ap_amm5)
+DEF (0x231, ARC_OPCODE_ARCALL, NONE, ap_ac5)
+DEF (0x232, ARC_OPCODE_ARCALL, NONE, ap_amv6)
+DEF (0x233, ARC_OPCODE_ARCALL, NONE, ap_amm6)
+DEF (0x234, ARC_OPCODE_ARCALL, NONE, ap_ac6)
+DEF (0x235, ARC_OPCODE_ARCALL, NONE, ap_amv7)
+DEF (0x236, ARC_OPCODE_ARCALL, NONE, ap_amm7)
+DEF (0x237, ARC_OPCODE_ARCALL, NONE, ap_ac7)
+DEF (0x278, ARC_OPCODE_ARCALL, NONE, pct_control)
+DEF (0x279, ARC_OPCODE_ARCALL, NONE, pct_bank)
+DEF (0x300, ARC_OPCODE_ARCFPX, DPX,  fp_status)
+DEF (0x301, ARC_OPCODE_ARCFPX, DPX,  aux_dpfp1l)
+DEF (0x301, ARC_OPCODE_ARCFPX, DPX,  d1l)
+DEF (0x302, ARC_OPCODE_ARCFPX, DPX,  aux_dpfp1h)
+DEF (0x302, ARC_OPCODE_ARCFPX, DPX,  d1h)
+DEF (0x302, ARC_OPCODE_ARCv2EM, DPA,  d1l)
+DEF (0x303, ARC_OPCODE_ARCFPX, DPX,  aux_dpfp2l)
+DEF (0x303, ARC_OPCODE_ARCFPX, DPX,  d2l)
+DEF (0x303, ARC_OPCODE_ARCv2EM, DPA,  d1h)
+DEF (0x304, ARC_OPCODE_ARCFPX, DPX,  aux_dpfp2h)
+DEF (0x304, ARC_OPCODE_ARCFPX, DPX,  d2h)
+DEF (0x304, ARC_OPCODE_ARCv2EM, DPA,  d2l)
+DEF (0x305, ARC_OPCODE_ARCFPX, DPX,  dpfp_status)
+DEF (0x305, ARC_OPCODE_ARCv2EM, DPA,  d2h)
+DEF (0x306, ARC_OPCODE_ARCALL, NONE, rtt)
+DEF (0x400, ARC_OPCODE_ARCALL, NONE, eret)
+DEF (0x401, ARC_OPCODE_ARCALL, NONE, erbta)
+DEF (0x402, ARC_OPCODE_ARCALL, NONE, erstatus)
+DEF (0x403, ARC_OPCODE_ARCALL, NONE, ecr)
+DEF (0x404, ARC_OPCODE_ARCALL, NONE, efa)
+DEF (0x405, ARC_OPCODE_ARCALL, NONE, tlbpd0)
+DEF (0x406, ARC_OPCODE_ARCALL, NONE, tlbpd1)
+DEF (0x407, ARC_OPCODE_ARCALL, NONE, tlbindex)
+DEF (0x408, ARC_OPCODE_ARCALL, NONE, tlbcommand)
+DEF (0x409, ARC_OPCODE_ARCALL, NONE, pid)
+DEF (0x409, ARC_OPCODE_ARCALL, NONE, mpuen)
+DEF (0x40a, ARC_OPCODE_ARCALL, NONE, icause1)
+DEF (0x40b, ARC_OPCODE_ARCALL, NONE, icause2)
+DEF (0x40c, ARC_OPCODE_ARCALL, NONE, aux_ienable)
+DEF (0x40d, ARC_OPCODE_ARCALL, NONE, aux_itrigger)
+DEF (0x410, ARC_OPCODE_ARCALL, NONE, xpu)
+DEF (0x412, ARC_OPCODE_ARCALL, NONE, bta)
+DEF (0x413, ARC_OPCODE_ARCALL, NONE, bta_l1)
+DEF (0x414, ARC_OPCODE_ARCALL, NONE, bta_l2)
+DEF (0x415, ARC_OPCODE_ARCALL, NONE, aux_irq_pulse_cancel)
+DEF (0x416, ARC_OPCODE_ARCALL, NONE, aux_irq_pending)
+DEF (0x418, ARC_OPCODE_ARCALL, NONE, scratch_data0)
+DEF (0x420, ARC_OPCODE_ARCALL, NONE, mpuic)
+DEF (0x421, ARC_OPCODE_ARCALL, NONE, mpufa)
+DEF (0x422, ARC_OPCODE_ARCALL, NONE, mpurdb0)
+DEF (0x423, ARC_OPCODE_ARCALL, NONE, mpurdp0)
+DEF (0x424, ARC_OPCODE_ARCALL, NONE, mpurdb1)
+DEF (0x425, ARC_OPCODE_ARCALL, NONE, mpurdp1)
+DEF (0x426, ARC_OPCODE_ARCALL, NONE, mpurdb2)
+DEF (0x427, ARC_OPCODE_ARCALL, NONE, mpurdp2)
+DEF (0x428, ARC_OPCODE_ARCALL, NONE, mpurdb3)
+DEF (0x429, ARC_OPCODE_ARCALL, NONE, mpurdp3)
+DEF (0x42a, ARC_OPCODE_ARCALL, NONE, mpurdb4)
+DEF (0x42b, ARC_OPCODE_ARCALL, NONE, mpurdp4)
+DEF (0x42c, ARC_OPCODE_ARCALL, NONE, mpurdb5)
+DEF (0x42d, ARC_OPCODE_ARCALL, NONE, mpurdp5)
+DEF (0x42e, ARC_OPCODE_ARCALL, NONE, mpurdb6)
+DEF (0x42f, ARC_OPCODE_ARCALL, NONE, mpurdp6)
+DEF (0x430, ARC_OPCODE_ARCALL, NONE, mpurdb7)
+DEF (0x431, ARC_OPCODE_ARCALL, NONE, mpurdp7)
+DEF (0x432, ARC_OPCODE_ARCALL, NONE, mpurdb8)
+DEF (0x433, ARC_OPCODE_ARCALL, NONE, mpurdp8)
+DEF (0x434, ARC_OPCODE_ARCALL, NONE, mpurdb9)
+DEF (0x435, ARC_OPCODE_ARCALL, NONE, mpurdp9)
+DEF (0x436, ARC_OPCODE_ARCALL, NONE, mpurdb10)
+DEF (0x437, ARC_OPCODE_ARCALL, NONE, mpurdp10)
+DEF (0x438, ARC_OPCODE_ARCALL, NONE, mpurdb11)
+DEF (0x439, ARC_OPCODE_ARCALL, NONE, mpurdp11)
+DEF (0x43a, ARC_OPCODE_ARCALL, NONE, mpurdb12)
+DEF (0x43b, ARC_OPCODE_ARCALL, NONE, mpurdp12)
+DEF (0x43c, ARC_OPCODE_ARCALL, NONE, mpurdb13)
+DEF (0x43d, ARC_OPCODE_ARCALL, NONE, mpurdp13)
+DEF (0x43e, ARC_OPCODE_ARCALL, NONE, mpurdb14)
+DEF (0x43f, ARC_OPCODE_ARCALL, NONE, mpurdp14)
+DEF (0x440, ARC_OPCODE_ARCALL, NONE, mpurdb15)
+DEF (0x441, ARC_OPCODE_ARCALL, NONE, mpurdp15)
+DEF (0x44f, ARC_OPCODE_ARCALL, NONE, eia_flags)
+DEF (0x450, ARC_OPCODE_ARCALL, NONE, pm_status)
+DEF (0x451, ARC_OPCODE_ARCALL, NONE, wake)
+DEF (0x452, ARC_OPCODE_ARCALL, NONE, dvfs_performance)
+DEF (0x453, ARC_OPCODE_ARCALL, NONE, pwr_ctrl)
+DEF (0x500, ARC_OPCODE_ARCALL, NONE, aux_vlc_buf_idx)
+DEF (0x501, ARC_OPCODE_ARCALL, NONE, aux_vlc_read_buf)
+DEF (0x502, ARC_OPCODE_ARCALL, NONE, aux_vlc_valid_bits)
+DEF (0x503, ARC_OPCODE_ARCALL, NONE, aux_vlc_buf_in)
+DEF (0x504, ARC_OPCODE_ARCALL, NONE, aux_vlc_buf_free)
+DEF (0x505, ARC_OPCODE_ARCALL, NONE, aux_vlc_ibuf_status)
+DEF (0x506, ARC_OPCODE_ARCALL, NONE, aux_vlc_setup)
+DEF (0x507, ARC_OPCODE_ARCALL, NONE, aux_vlc_bits)
+DEF (0x508, ARC_OPCODE_ARCALL, NONE, aux_vlc_table)
+DEF (0x509, ARC_OPCODE_ARCALL, NONE, aux_vlc_get_symbol)
+DEF (0x50a, ARC_OPCODE_ARCALL, NONE, aux_vlc_read_symbol)
+DEF (0x510, ARC_OPCODE_ARCALL, NONE, aux_ucavlc_setup)
+DEF (0x511, ARC_OPCODE_ARCALL, NONE, aux_ucavlc_state)
+DEF (0x512, ARC_OPCODE_ARCALL, NONE, aux_cavlc_zero_left)
+DEF (0x514, ARC_OPCODE_ARCALL, NONE, aux_uvlc_i_state)
+DEF (0x51c, ARC_OPCODE_ARCALL, NONE, aux_vlc_dma_ptr)
+DEF (0x51d, ARC_OPCODE_ARCALL, NONE, aux_vlc_dma_end)
+DEF (0x51e, ARC_OPCODE_ARCALL, NONE, aux_vlc_dma_esc)
+DEF (0x51f, ARC_OPCODE_ARCALL, NONE, aux_vlc_dma_ctrl)
+DEF (0x520, ARC_OPCODE_ARCALL, NONE, aux_vlc_get_0bit)
+DEF (0x521, ARC_OPCODE_ARCALL, NONE, aux_vlc_get_1bit)
+DEF (0x522, ARC_OPCODE_ARCALL, NONE, aux_vlc_get_2bit)
+DEF (0x523, ARC_OPCODE_ARCALL, NONE, aux_vlc_get_3bit)
+DEF (0x524, ARC_OPCODE_ARCALL, NONE, aux_vlc_get_4bit)
+DEF (0x525, ARC_OPCODE_ARCALL, NONE, aux_vlc_get_5bit)
+DEF (0x526, ARC_OPCODE_ARCALL, NONE, aux_vlc_get_6bit)
+DEF (0x527, ARC_OPCODE_ARCALL, NONE, aux_vlc_get_7bit)
+DEF (0x528, ARC_OPCODE_ARCALL, NONE, aux_vlc_get_8bit)
+DEF (0x529, ARC_OPCODE_ARCALL, NONE, aux_vlc_get_9bit)
+DEF (0x52a, ARC_OPCODE_ARCALL, NONE, aux_vlc_get_10bit)
+DEF (0x52b, ARC_OPCODE_ARCALL, NONE, aux_vlc_get_11bit)
+DEF (0x52c, ARC_OPCODE_ARCALL, NONE, aux_vlc_get_12bit)
+DEF (0x52d, ARC_OPCODE_ARCALL, NONE, aux_vlc_get_13bit)
+DEF (0x52e, ARC_OPCODE_ARCALL, NONE, aux_vlc_get_14bit)
+DEF (0x52f, ARC_OPCODE_ARCALL, NONE, aux_vlc_get_15bit)
+DEF (0x530, ARC_OPCODE_ARCALL, NONE, aux_vlc_get_16bit)
+DEF (0x531, ARC_OPCODE_ARCALL, NONE, aux_vlc_get_17bit)
+DEF (0x532, ARC_OPCODE_ARCALL, NONE, aux_vlc_get_18bit)
+DEF (0x533, ARC_OPCODE_ARCALL, NONE, aux_vlc_get_19bit)
+DEF (0x534, ARC_OPCODE_ARCALL, NONE, aux_vlc_get_20bit)
+DEF (0x535, ARC_OPCODE_ARCALL, NONE, aux_vlc_get_21bit)
+DEF (0x536, ARC_OPCODE_ARCALL, NONE, aux_vlc_get_22bit)
+DEF (0x537, ARC_OPCODE_ARCALL, NONE, aux_vlc_get_23bit)
+DEF (0x538, ARC_OPCODE_ARCALL, NONE, aux_vlc_get_24bit)
+DEF (0x539, ARC_OPCODE_ARCALL, NONE, aux_vlc_get_25bit)
+DEF (0x53a, ARC_OPCODE_ARCALL, NONE, aux_vlc_get_26bit)
+DEF (0x53b, ARC_OPCODE_ARCALL, NONE, aux_vlc_get_27bit)
+DEF (0x53c, ARC_OPCODE_ARCALL, NONE, aux_vlc_get_28bit)
+DEF (0x53d, ARC_OPCODE_ARCALL, NONE, aux_vlc_get_29bit)
+DEF (0x53e, ARC_OPCODE_ARCALL, NONE, aux_vlc_get_30bit)
+DEF (0x53f, ARC_OPCODE_ARCALL, NONE, aux_vlc_get_31bit)
+DEF (0x540, ARC_OPCODE_ARCALL, NONE, aux_cabac_ctrl)
+DEF (0x541, ARC_OPCODE_ARCALL, NONE, aux_cabac_ctx_state)
+DEF (0x542, ARC_OPCODE_ARCALL, NONE, aux_cabac_cod_param)
+DEF (0x543, ARC_OPCODE_ARCALL, NONE, aux_cabac_misc0)
+DEF (0x544, ARC_OPCODE_ARCALL, NONE, aux_cabac_misc1)
+DEF (0x545, ARC_OPCODE_ARCALL, NONE, aux_cabac_misc2)
+DEF (0x700, ARC_OPCODE_ARCALL, NONE, smart_control)
+DEF (0x701, ARC_OPCODE_ARCALL, NONE, smart_data_0)
+DEF (0x701, ARC_OPCODE_ARCALL, NONE, smart_data_1)
+DEF (0x701, ARC_OPCODE_ARCALL, NONE, smart_data_2)
+DEF (0x701, ARC_OPCODE_ARCALL, NONE, smart_data_3)