diff options
author | Jan Beulich <jbeulich@suse.com> | 2024-01-19 10:18:32 +0100 |
---|---|---|
committer | Jan Beulich <jbeulich@suse.com> | 2024-01-19 10:18:32 +0100 |
commit | eea4357967b6182459d423c4d919a7cb0219604b (patch) | |
tree | 4dc5a7e8206da788bc09c06871cc5975ae9ca5b4 | |
parent | 2519809009ed5e250ad9ed9b6184d9c45dba5029 (diff) | |
download | gdb-eea4357967b6182459d423c4d919a7cb0219604b.zip gdb-eea4357967b6182459d423c4d919a7cb0219604b.tar.gz gdb-eea4357967b6182459d423c4d919a7cb0219604b.tar.bz2 |
x86/APX: VROUND{P,S}{S,D} can generally be encoded
VRNDSCALE{P,S}{S,D} is the AVX512 generalization of these AVX insns. As
long as the immediate has the top 4 bits clear, they are equivalent to
the earlier VEX-encoded insns, and hence can be used to permit use of
eGPR-s in the memory operand. Since this is the normal way of using
these insns, also alter the resulting diagnostic to complain about the
immediate, not the eGPR use.
-rw-r--r-- | gas/config/tc-i386.c | 6 | ||||
-rw-r--r-- | gas/testsuite/gas/i386/x86-64-apx-egpr-inval.l | 8 | ||||
-rw-r--r-- | gas/testsuite/gas/i386/x86-64-apx-egpr-inval.s | 8 | ||||
-rw-r--r-- | gas/testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d | 4 | ||||
-rw-r--r-- | gas/testsuite/gas/i386/x86-64-apx-evex-promoted.d | 4 | ||||
-rw-r--r-- | gas/testsuite/gas/i386/x86-64-apx-evex-promoted.s | 4 | ||||
-rw-r--r-- | opcodes/i386-opc.tbl | 4 | ||||
-rw-r--r-- | opcodes/i386-tbl.h | 346 |
8 files changed, 227 insertions, 157 deletions
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 4262e1e..51166ef 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -8156,7 +8156,8 @@ check_VecOperands (const insn_template *t) } /* Check the special Imm4 cases; must be the first operand. */ - if (is_cpu (t, CpuXOP) && t->operands == 5) + if ((is_cpu (t, CpuXOP) && t->operands == 5) + || (is_cpu (t, CpuAPX_F) && t->opcode_space == SPACE_0F3A)) { if (i.op[0].imms->X_op != O_constant || !fits_in_imm4 (i.op[0].imms->X_add_number)) @@ -8166,7 +8167,8 @@ check_VecOperands (const insn_template *t) } /* Turn off Imm<N> so that update_imm won't complain. */ - operand_type_set (&i.types[0], 0); + if (t->operands == 5) + operand_type_set (&i.types[0], 0); } /* Check vector Disp8 operand. */ diff --git a/gas/testsuite/gas/i386/x86-64-apx-egpr-inval.l b/gas/testsuite/gas/i386/x86-64-apx-egpr-inval.l index 0472748..5cabe61 100644 --- a/gas/testsuite/gas/i386/x86-64-apx-egpr-inval.l +++ b/gas/testsuite/gas/i386/x86-64-apx-egpr-inval.l @@ -187,10 +187,10 @@ .*:195: Error: extended GPR cannot be used as base/index for `vrcpps' .*:196: Error: extended GPR cannot be used as base/index for `vrcpps' .*:197: Error: extended GPR cannot be used as base/index for `vrcpss' -.*:198: Error: extended GPR cannot be used as base/index for `vroundpd' -.*:199: Error: extended GPR cannot be used as base/index for `vroundps' -.*:200: Error: extended GPR cannot be used as base/index for `vroundsd' -.*:201: Error: extended GPR cannot be used as base/index for `vroundss' +.*:198: Error: .* 4 bits for `vroundpd' +.*:199: Error: .* 4 bits for `vroundps' +.*:200: Error: .* 4 bits for `vroundsd' +.*:201: Error: .* 4 bits for `vroundss' .*:202: Error: extended GPR cannot be used as base/index for `vrsqrtps' .*:203: Error: extended GPR cannot be used as base/index for `vrsqrtps' .*:204: Error: extended GPR cannot be used as base/index for `vrsqrtss' diff --git a/gas/testsuite/gas/i386/x86-64-apx-egpr-inval.s b/gas/testsuite/gas/i386/x86-64-apx-egpr-inval.s index fde038d..76f0a1b 100644 --- a/gas/testsuite/gas/i386/x86-64-apx-egpr-inval.s +++ b/gas/testsuite/gas/i386/x86-64-apx-egpr-inval.s @@ -195,10 +195,10 @@ vrcpps (%r27),%xmm6 vrcpps (%r27),%ymm6 vrcpss (%r27),%xmm6,%xmm6 - vroundpd $1,(%r24),%xmm6 - vroundps $2,(%r24),%xmm6 - vroundsd $3,(%r24),%xmm6,%xmm3 - vroundss $4,(%r24),%xmm6,%xmm3 + vroundpd $0x11,(%r24),%xmm6 + vroundps $0x22,(%r24),%xmm6 + vroundsd $0x33,(%r24),%xmm6,%xmm3 + vroundss $0x44,(%r24),%xmm6,%xmm3 vrsqrtps (%r27),%xmm6 vrsqrtps (%r27),%ymm6 vrsqrtss (%r27),%xmm6,%xmm6 diff --git a/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d b/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d index 02e811d..354c85c 100644 --- a/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d +++ b/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d @@ -158,6 +158,10 @@ Disassembly of section \.text: [ ]*[a-f0-9]+:[ ]*62 da 7f 08 4b b4 87 23 01 00 00[ ]+tileloadd tmm6,\[r31\+rax\*4\+0x123\] [ ]*[a-f0-9]+:[ ]*62 da 7d 08 4b b4 87 23 01 00 00[ ]+tileloaddt1 tmm6,\[r31\+rax\*4\+0x123\] [ ]*[a-f0-9]+:[ ]*62 da 7e 08 4b b4 87 23 01 00 00[ ]+tilestored[ ]+\[r31\+rax\*4\+0x123\],tmm6 +[ ]*[a-f0-9]+:[ ]*62 db fd 08 09 30 01[ ]+vrndscalepd xmm6,XMMWORD PTR \[r24\],(0x)?1 +[ ]*[a-f0-9]+:[ ]*62 db 7d 08 08 30 02[ ]+vrndscaleps xmm6,XMMWORD PTR \[r24\],(0x)?2 +[ ]*[a-f0-9]+:[ ]*62 db cd 08 0b 18 03[ ]+vrndscalesd xmm3,xmm6,QWORD PTR \[r24\],(0x)?3 +[ ]*[a-f0-9]+:[ ]*62 db 4d 08 0a 18 04[ ]+vrndscaless xmm3,xmm6,DWORD PTR \[r24\],(0x)?4 [ ]*[a-f0-9]+:[ ]*62 4c 7c 08 66 8c 87 23 01 00 00[ ]+wrssd[ ]+\[r31\+rax\*4\+0x123\],r25d [ ]*[a-f0-9]+:[ ]*62 4c fc 08 66 bc 87 23 01 00 00[ ]+wrssq[ ]+\[r31\+rax\*4\+0x123\],r31 [ ]*[a-f0-9]+:[ ]*62 4c 7d 08 65 8c 87 23 01 00 00[ ]+wrussd[ ]+\[r31\+rax\*4\+0x123\],r25d diff --git a/gas/testsuite/gas/i386/x86-64-apx-evex-promoted.d b/gas/testsuite/gas/i386/x86-64-apx-evex-promoted.d index 3a7dffc..a86fa60 100644 --- a/gas/testsuite/gas/i386/x86-64-apx-evex-promoted.d +++ b/gas/testsuite/gas/i386/x86-64-apx-evex-promoted.d @@ -158,6 +158,10 @@ Disassembly of section \.text: [ ]*[a-f0-9]+:[ ]*62 da 7f 08 4b b4 87 23 01 00 00[ ]+tileloadd[ ]+0x123\(%r31,%rax,4\),%tmm6 [ ]*[a-f0-9]+:[ ]*62 da 7d 08 4b b4 87 23 01 00 00[ ]+tileloaddt1[ ]+0x123\(%r31,%rax,4\),%tmm6 [ ]*[a-f0-9]+:[ ]*62 da 7e 08 4b b4 87 23 01 00 00[ ]+tilestored[ ]+%tmm6,0x123\(%r31,%rax,4\) +[ ]*[a-f0-9]+:[ ]*62 db fd 08 09 30 01[ ]+vrndscalepd \$0x1,\(%r24\),%xmm6 +[ ]*[a-f0-9]+:[ ]*62 db 7d 08 08 30 02[ ]+vrndscaleps \$0x2,\(%r24\),%xmm6 +[ ]*[a-f0-9]+:[ ]*62 db cd 08 0b 18 03[ ]+vrndscalesd \$0x3,\(%r24\),%xmm6,%xmm3 +[ ]*[a-f0-9]+:[ ]*62 db 4d 08 0a 18 04[ ]+vrndscaless \$0x4,\(%r24\),%xmm6,%xmm3 [ ]*[a-f0-9]+:[ ]*62 4c 7c 08 66 8c 87 23 01 00 00[ ]+wrssd[ ]+%r25d,0x123\(%r31,%rax,4\) [ ]*[a-f0-9]+:[ ]*62 4c fc 08 66 bc 87 23 01 00 00[ ]+wrssq[ ]+%r31,0x123\(%r31,%rax,4\) [ ]*[a-f0-9]+:[ ]*62 4c 7d 08 65 8c 87 23 01 00 00[ ]+wrussd[ ]+%r25d,0x123\(%r31,%rax,4\) diff --git a/gas/testsuite/gas/i386/x86-64-apx-evex-promoted.s b/gas/testsuite/gas/i386/x86-64-apx-evex-promoted.s index 39752c2..ac536d3 100644 --- a/gas/testsuite/gas/i386/x86-64-apx-evex-promoted.s +++ b/gas/testsuite/gas/i386/x86-64-apx-evex-promoted.s @@ -152,6 +152,10 @@ _start: tileloadd 0x123(%r31,%rax,4),%tmm6 tileloaddt1 0x123(%r31,%rax,4),%tmm6 tilestored %tmm6,0x123(%r31,%rax,4) + vroundpd $1,(%r24),%xmm6 + vroundps $2,(%r24),%xmm6 + vroundsd $3,(%r24),%xmm6,%xmm3 + vroundss $4,(%r24),%xmm6,%xmm3 wrssd %r25d,0x123(%r31,%rax,4) wrssq %r31,0x123(%r31,%rax,4) wrussd %r25d,0x123(%r31,%rax,4) diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 11a77a7..717e208 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -1790,6 +1790,10 @@ vrcpps, 0x53, AVX, Modrm|Vex|Space0F|VexWIG|CheckOperandSize|NoSuf, { Unspecifie vrcpss, 0xf353, AVX, Modrm|Vex=3|Space0F|VexVVVV|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } vroundp<sd>, 0x6608 | <sd:opc>, AVX, Modrm|Vex|Space0F3A|VexWIG|CheckOperandSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } vrounds<sd>, 0x660a | <sd:opc>, AVX, Modrm|VexLIG|Space0F3A|VexVVVV|VexWIG|NoSuf, { Imm8, <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +// These are really clones of VRNDSCALE{P,S}{S,D}, with broadcast, masking, SAE, +// 512-bit operand size, and register sources dropped. +vroundp<sd>, 0x6608 | <sd:opc>, APX_F, Modrm|Space0F3A|<sd:vexw>|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM } +vrounds<sd>, 0x660a | <sd:opc>, APX_F, Modrm|EVexLIG|Space0F3A|VexVVVV|<sd:vexw>|Disp8MemShift|NoSuf, { Imm8, <sd:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } vrsqrtps, 0x52, AVX, Modrm|Vex|Space0F|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } vrsqrtss, 0xf352, AVX, Modrm|Vex=3|Space0F|VexVVVV|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } vshufp<sd>, 0x<sd:ppfx>c6, AVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h index c0aab67..72d5b9f 100644 --- a/opcodes/i386-tbl.h +++ b/opcodes/i386-tbl.h @@ -25292,6 +25292,18 @@ static const insn_template i386_optab[] = 1, 1, 0, 0, 1, 0 } }, { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0 } } } }, + { MN_vroundps, 0x08 | 0, 3, SPACE_0F3A, None, + { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 1, 1, 0, 0, 5, 0, 0, 0, 0, 7, 0, 0, 0, 0, 0, + 0 }, + { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, + 1, 1, 0, 0, 1, 0 } }, + { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 0, 0, 0, 0 } } } }, { MN_vroundpd, 0x08 | 1, 3, SPACE_0F3A, None, { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 3, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, @@ -25304,6 +25316,18 @@ static const insn_template i386_optab[] = 1, 1, 0, 0, 1, 0 } }, { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0 } } } }, + { MN_vroundpd, 0x08 | 1, 3, SPACE_0F3A, None, + { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 2, 1, 0, 0, 5, 0, 0, 0, 0, 7, 0, 0, 0, 0, 0, + 0 }, + { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, + 1, 1, 0, 0, 1, 0 } }, + { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 0, 0, 0, 0 } } } }, { MN_vroundss, 0x0a | 0, 4, SPACE_0F3A, None, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 3, 1, 3, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, @@ -25318,6 +25342,20 @@ static const insn_template i386_optab[] = 1, 0, 0, 0, 0, 0 } }, { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } } } }, + { MN_vroundss, 0x0a | 0, 4, SPACE_0F3A, None, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 1, 1, 1, 0, 0, 4, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, + 0 }, + { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 0, 0, + 0, 0, 0, 0, 1, 0 } }, + { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 0, 0, 0, 0 } }, + { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 0, 0, 0, 0 } } } }, { MN_vroundsd, 0x0a | 1, 4, SPACE_0F3A, None, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 3, 1, 3, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, @@ -25332,6 +25370,20 @@ static const insn_template i386_optab[] = 1, 0, 0, 0, 0, 0 } }, { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } } } }, + { MN_vroundsd, 0x0a | 1, 4, SPACE_0F3A, None, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 1, 2, 1, 0, 0, 4, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, + 0 }, + { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, + 0, 0, 0, 0, 1, 0 } }, + { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 0, 0, 0, 0 } }, + { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 0, 0, 0, 0 } } } }, { MN_vrsqrtps, 0x52, 2, SPACE_0F, None, { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, @@ -41396,153 +41448,153 @@ static const i386_op_off_t i386_op_sets[] = 2373, 2377, 2379, 2383, 2387, 2391, 2395, 2399, 2401, 2405, 2407, 2409, 2411, 2413, 2415, 2417, 2419, 2421, 2422, 2424, 2426, 2428, 2430, 2432, - 2434, 2436, 2438, 2439, 2440, 2441, 2442, 2443, - 2444, 2445, 2446, 2447, 2449, 2451, 2453, 2455, - 2457, 2459, 2460, 2462, 2464, 2466, 2468, 2469, - 2470, 2472, 2474, 2476, 2478, 2480, 2482, 2484, - 2486, 2487, 2488, 2489, 2490, 2493, 2496, 2498, - 2501, 2502, 2503, 2505, 2506, 2508, 2509, 2510, - 2512, 2514, 2515, 2516, 2517, 2518, 2519, 2522, - 2527, 2532, 2537, 2542, 2545, 2550, 2555, 2557, - 2559, 2561, 2563, 2564, 2565, 2567, 2569, 2571, - 2573, 2575, 2577, 2579, 2580, 2581, 2582, 2583, - 2584, 2585, 2590, 2595, 2596, 2597, 2598, 2599, - 2600, 2601, 2602, 2603, 2604, 2605, 2606, 2607, - 2608, 2609, 2610, 2611, 2612, 2613, 2614, 2615, - 2616, 2617, 2618, 2619, 2620, 2621, 2622, 2623, - 2624, 2625, 2626, 2627, 2628, 2629, 2630, 2631, - 2632, 2633, 2634, 2635, 2636, 2637, 2638, 2639, - 2640, 2641, 2642, 2643, 2644, 2645, 2646, 2647, - 2648, 2649, 2650, 2651, 2652, 2653, 2654, 2655, - 2656, 2657, 2658, 2659, 2660, 2661, 2662, 2663, - 2664, 2665, 2666, 2667, 2668, 2669, 2670, 2671, - 2672, 2673, 2674, 2675, 2676, 2677, 2678, 2679, - 2680, 2681, 2682, 2683, 2684, 2685, 2686, 2687, - 2688, 2689, 2690, 2691, 2692, 2693, 2694, 2695, - 2696, 2697, 2698, 2699, 2700, 2701, 2702, 2703, - 2704, 2705, 2706, 2707, 2708, 2709, 2710, 2711, - 2712, 2713, 2714, 2715, 2716, 2717, 2718, 2719, - 2720, 2721, 2722, 2723, 2724, 2725, 2726, 2727, - 2728, 2729, 2730, 2731, 2732, 2733, 2734, 2735, - 2736, 2737, 2738, 2739, 2740, 2741, 2742, 2743, - 2744, 2745, 2746, 2747, 2748, 2749, 2750, 2751, - 2752, 2753, 2754, 2755, 2756, 2757, 2758, 2759, - 2760, 2761, 2762, 2763, 2764, 2765, 2766, 2767, - 2768, 2769, 2770, 2771, 2772, 2773, 2774, 2775, - 2776, 2777, 2778, 2779, 2780, 2781, 2782, 2783, - 2784, 2785, 2786, 2787, 2788, 2789, 2790, 2791, - 2792, 2793, 2794, 2795, 2796, 2798, 2800, 2801, - 2802, 2803, 2804, 2805, 2806, 2807, 2808, 2809, - 2810, 2811, 2812, 2813, 2814, 2815, 2816, 2817, - 2818, 2819, 2820, 2821, 2822, 2823, 2824, 2825, - 2826, 2827, 2828, 2830, 2832, 2834, 2836, 2837, - 2838, 2839, 2840, 2841, 2842, 2843, 2844, 2845, - 2846, 2847, 2848, 2849, 2851, 2852, 2853, 2854, - 2855, 2856, 2857, 2858, 2859, 2860, 2861, 2862, - 2863, 2864, 2865, 2866, 2867, 2868, 2869, 2870, - 2871, 2872, 2873, 2874, 2875, 2876, 2877, 2878, - 2879, 2880, 2881, 2882, 2883, 2884, 2885, 2886, - 2887, 2888, 2889, 2890, 2891, 2892, 2893, 2894, - 2895, 2896, 2898, 2900, 2901, 2902, 2904, 2905, - 2907, 2909, 2910, 2911, 2913, 2915, 2916, 2917, - 2918, 2919, 2920, 2921, 2922, 2923, 2924, 2925, - 2926, 2927, 2928, 2929, 2930, 2931, 2932, 2933, - 2936, 2939, 2940, 2941, 2942, 2943, 2944, 2945, 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3680, 3681, 3682, 3683, 3684, + 3685, 3686, 3687, 3688, 3689, 3690, 3691, 3692, + 3693, 3694, 3695, 3696, 3697, 3698, 3699, 3700, + 3701, 3702, 3703, 3704, 3705, 3706, 3707, 3708, + 3709, 3710, 3711, 3712, 3713, 3714, 3715, 3716, + 3717, 3718, 3719, 3720, 3721, 3722, 3723, 3724, + 3725, 3726, 3727, 3728, 3729, 3730, 3731, 3732, + 3733, 3734, 3735, 3736, 3737, 3738, 3739, 3740, + 3741, 3742, 3743, 3744, 3745, 3746, 3747, 3750, + 3751, 3752, 3755, 3756, 3757, 3759, 3760, 3761, + 3762, 3764, 3765, 3766, 3767, 3769, 3770, 3771, + 3772, 3775, 3776, 3777, 3778, 3779, 3782, 3785, + 3788, 3791, 3794, 3795, 3796, 3797, 3798, 3800, + 3802, 3803, 3804, 3805, 3808, 3811, 3814, 3817, + 3820, 3821, 3822, 3823, 3825, 3826, 3827, 3828, + 3830, 3831, 3832, 3833, 3834, 3835, 3836, 3837, + 3838, 3839, 3840, 3841, 3842, 3843, 3844, 3845, + 3846, 3847, 3848, 3849, 3850, 3851, 3852, 3853, + 3854, 3855, 3856, 3857, 3858, 3859, 3860, 3861, + 3862, 3863, 3864, 3865, 3866, 3867, 3868, 3869, + 3871, 3873, 3875, 3877, 3879, 3880, 3881, 3884, + 3887, 3888, 3889, 3890, 3891 }; /* i386 mnemonics table. */ |