x86: AVX512 extract/insert insns need to honor EVEX.L'L

Just like their AVX counterparts do for VEX.L.

At this occasion also make EVEX.W have the same effect as VEX.W on the
printing of VPINSR{B,W}'s operands, bringing them also in sync with
VPEXTR{B,W}.

10 files changed, 120 insertions, 45 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index db578b7..f7a66b0 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,13 @@
 2020-07-06  Jan Beulich  <jbeulich@suse.com>
 
+	* testsuite/gas/i386/x86-64-avx512bw-wig1.d,
+	testsuite/gas/i386/x86-64-avx512bw-wig1-intel.d,
+	testsuite/gas/i386/x86-64-evex-wig1.d,
+	testsuite/gas/i386/x86-64-evex-wig1-intel.d: Adjust
+	expectations.
+
+2020-07-06  Jan Beulich  <jbeulich@suse.com>
+
 	* testsuite/gas/i386/avx512f-opts.s: Add EVEX movq tests.
 	* testsuite/gas/i386/x86-64-avx512f-opts.s: Add blank line.
 	* testsuite/gas/i386/avx512f-opts-intel.d,
diff --git a/gas/testsuite/gas/i386/x86-64-avx512bw-wig1-intel.d b/gas/testsuite/gas/i386/x86-64-avx512bw-wig1-intel.d
index 23876eb..79b0fdc 100644
--- a/gas/testsuite/gas/i386/x86-64-avx512bw-wig1-intel.d
+++ b/gas/testsuite/gas/i386/x86-64-avx512bw-wig1-intel.d
@@ -177,20 +177,20 @@ Disassembly of section \.text:
 [ 	]*[a-f0-9]+:[ 	]*62 91 fd 08 c5 c6 ab[ 	]*vpextrw rax,xmm30,0xab
 [ 	]*[a-f0-9]+:[ 	]*62 91 fd 08 c5 c6 7b[ 	]*vpextrw rax,xmm30,0x7b
 [ 	]*[a-f0-9]+:[ 	]*62 11 fd 08 c5 c6 7b[ 	]*vpextrw r8,xmm30,0x7b
-[ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 f0 ab[ 	]*vpinsrb xmm30,xmm29,eax,0xab
-[ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 f0 7b[ 	]*vpinsrb xmm30,xmm29,eax,0x7b
-[ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 f5 7b[ 	]*vpinsrb xmm30,xmm29,ebp,0x7b
-[ 	]*[a-f0-9]+:[ 	]*62 43 95 00 20 f5 7b[ 	]*vpinsrb xmm30,xmm29,r13d,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 f0 ab[ 	]*vpinsrb xmm30,xmm29,rax,0xab
+[ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 f0 7b[ 	]*vpinsrb xmm30,xmm29,rax,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 f5 7b[ 	]*vpinsrb xmm30,xmm29,rbp,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 43 95 00 20 f5 7b[ 	]*vpinsrb xmm30,xmm29,r13,0x7b
 [ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 31 7b[ 	]*vpinsrb xmm30,xmm29,BYTE PTR \[rcx\],0x7b
 [ 	]*[a-f0-9]+:[ 	]*62 23 95 00 20 b4 f0 23 01 00 00 7b[ 	]*vpinsrb xmm30,xmm29,BYTE PTR \[rax\+r14\*8\+0x123\],0x7b
 [ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 72 7f 7b[ 	]*vpinsrb xmm30,xmm29,BYTE PTR \[rdx\+0x7f\],0x7b
 [ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 b2 80 00 00 00 7b[ 	]*vpinsrb xmm30,xmm29,BYTE PTR \[rdx\+0x80\],0x7b
 [ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 72 80 7b[ 	]*vpinsrb xmm30,xmm29,BYTE PTR \[rdx-0x80\],0x7b
 [ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 b2 7f ff ff ff 7b[ 	]*vpinsrb xmm30,xmm29,BYTE PTR \[rdx-0x81\],0x7b
-[ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 f0 ab[ 	]*vpinsrw xmm30,xmm29,eax,0xab
-[ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 f0 7b[ 	]*vpinsrw xmm30,xmm29,eax,0x7b
-[ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 f5 7b[ 	]*vpinsrw xmm30,xmm29,ebp,0x7b
-[ 	]*[a-f0-9]+:[ 	]*62 41 95 00 c4 f5 7b[ 	]*vpinsrw xmm30,xmm29,r13d,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 f0 ab[ 	]*vpinsrw xmm30,xmm29,rax,0xab
+[ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 f0 7b[ 	]*vpinsrw xmm30,xmm29,rax,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 f5 7b[ 	]*vpinsrw xmm30,xmm29,rbp,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 41 95 00 c4 f5 7b[ 	]*vpinsrw xmm30,xmm29,r13,0x7b
 [ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 31 7b[ 	]*vpinsrw xmm30,xmm29,WORD PTR \[rcx\],0x7b
 [ 	]*[a-f0-9]+:[ 	]*62 21 95 00 c4 b4 f0 23 01 00 00 7b[ 	]*vpinsrw xmm30,xmm29,WORD PTR \[rax\+r14\*8\+0x123\],0x7b
 [ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 72 7f 7b[ 	]*vpinsrw xmm30,xmm29,WORD PTR \[rdx\+0xfe\],0x7b
@@ -708,20 +708,20 @@ Disassembly of section \.text:
 [ 	]*[a-f0-9]+:[ 	]*62 91 fd 08 c5 c6 ab[ 	]*vpextrw rax,xmm30,0xab
 [ 	]*[a-f0-9]+:[ 	]*62 91 fd 08 c5 c6 7b[ 	]*vpextrw rax,xmm30,0x7b
 [ 	]*[a-f0-9]+:[ 	]*62 11 fd 08 c5 c6 7b[ 	]*vpextrw r8,xmm30,0x7b
-[ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 f0 ab[ 	]*vpinsrb xmm30,xmm29,eax,0xab
-[ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 f0 7b[ 	]*vpinsrb xmm30,xmm29,eax,0x7b
-[ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 f5 7b[ 	]*vpinsrb xmm30,xmm29,ebp,0x7b
-[ 	]*[a-f0-9]+:[ 	]*62 43 95 00 20 f5 7b[ 	]*vpinsrb xmm30,xmm29,r13d,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 f0 ab[ 	]*vpinsrb xmm30,xmm29,rax,0xab
+[ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 f0 7b[ 	]*vpinsrb xmm30,xmm29,rax,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 f5 7b[ 	]*vpinsrb xmm30,xmm29,rbp,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 43 95 00 20 f5 7b[ 	]*vpinsrb xmm30,xmm29,r13,0x7b
 [ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 31 7b[ 	]*vpinsrb xmm30,xmm29,BYTE PTR \[rcx\],0x7b
 [ 	]*[a-f0-9]+:[ 	]*62 23 95 00 20 b4 f0 34 12 00 00 7b[ 	]*vpinsrb xmm30,xmm29,BYTE PTR \[rax\+r14\*8\+0x1234\],0x7b
 [ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 72 7f 7b[ 	]*vpinsrb xmm30,xmm29,BYTE PTR \[rdx\+0x7f\],0x7b
 [ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 b2 80 00 00 00 7b[ 	]*vpinsrb xmm30,xmm29,BYTE PTR \[rdx\+0x80\],0x7b
 [ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 72 80 7b[ 	]*vpinsrb xmm30,xmm29,BYTE PTR \[rdx-0x80\],0x7b
 [ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 b2 7f ff ff ff 7b[ 	]*vpinsrb xmm30,xmm29,BYTE PTR \[rdx-0x81\],0x7b
-[ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 f0 ab[ 	]*vpinsrw xmm30,xmm29,eax,0xab
-[ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 f0 7b[ 	]*vpinsrw xmm30,xmm29,eax,0x7b
-[ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 f5 7b[ 	]*vpinsrw xmm30,xmm29,ebp,0x7b
-[ 	]*[a-f0-9]+:[ 	]*62 41 95 00 c4 f5 7b[ 	]*vpinsrw xmm30,xmm29,r13d,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 f0 ab[ 	]*vpinsrw xmm30,xmm29,rax,0xab
+[ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 f0 7b[ 	]*vpinsrw xmm30,xmm29,rax,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 f5 7b[ 	]*vpinsrw xmm30,xmm29,rbp,0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 41 95 00 c4 f5 7b[ 	]*vpinsrw xmm30,xmm29,r13,0x7b
 [ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 31 7b[ 	]*vpinsrw xmm30,xmm29,WORD PTR \[rcx\],0x7b
 [ 	]*[a-f0-9]+:[ 	]*62 21 95 00 c4 b4 f0 34 12 00 00 7b[ 	]*vpinsrw xmm30,xmm29,WORD PTR \[rax\+r14\*8\+0x1234\],0x7b
 [ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 72 7f 7b[ 	]*vpinsrw xmm30,xmm29,WORD PTR \[rdx\+0xfe\],0x7b
diff --git a/gas/testsuite/gas/i386/x86-64-avx512bw-wig1.d b/gas/testsuite/gas/i386/x86-64-avx512bw-wig1.d
index 5954740..f48e5e6 100644
--- a/gas/testsuite/gas/i386/x86-64-avx512bw-wig1.d
+++ b/gas/testsuite/gas/i386/x86-64-avx512bw-wig1.d
@@ -177,20 +177,20 @@ Disassembly of section \.text:
 [ 	]*[a-f0-9]+:[ 	]*62 91 fd 08 c5 c6 ab[ 	]*vpextrw \$0xab,%xmm30,%rax
 [ 	]*[a-f0-9]+:[ 	]*62 91 fd 08 c5 c6 7b[ 	]*vpextrw \$0x7b,%xmm30,%rax
 [ 	]*[a-f0-9]+:[ 	]*62 11 fd 08 c5 c6 7b[ 	]*vpextrw \$0x7b,%xmm30,%r8
-[ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 f0 ab[ 	]*vpinsrb \$0xab,%eax,%xmm29,%xmm30
-[ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 f0 7b[ 	]*vpinsrb \$0x7b,%eax,%xmm29,%xmm30
-[ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 f5 7b[ 	]*vpinsrb \$0x7b,%ebp,%xmm29,%xmm30
-[ 	]*[a-f0-9]+:[ 	]*62 43 95 00 20 f5 7b[ 	]*vpinsrb \$0x7b,%r13d,%xmm29,%xmm30
+[ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 f0 ab[ 	]*vpinsrb \$0xab,%rax,%xmm29,%xmm30
+[ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 f0 7b[ 	]*vpinsrb \$0x7b,%rax,%xmm29,%xmm30
+[ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 f5 7b[ 	]*vpinsrb \$0x7b,%rbp,%xmm29,%xmm30
+[ 	]*[a-f0-9]+:[ 	]*62 43 95 00 20 f5 7b[ 	]*vpinsrb \$0x7b,%r13,%xmm29,%xmm30
 [ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 31 7b[ 	]*vpinsrb \$0x7b,\(%rcx\),%xmm29,%xmm30
 [ 	]*[a-f0-9]+:[ 	]*62 23 95 00 20 b4 f0 23 01 00 00 7b[ 	]*vpinsrb \$0x7b,0x123\(%rax,%r14,8\),%xmm29,%xmm30
 [ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 72 7f 7b[ 	]*vpinsrb \$0x7b,0x7f\(%rdx\),%xmm29,%xmm30
 [ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 b2 80 00 00 00 7b[ 	]*vpinsrb \$0x7b,0x80\(%rdx\),%xmm29,%xmm30
 [ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 72 80 7b[ 	]*vpinsrb \$0x7b,-0x80\(%rdx\),%xmm29,%xmm30
 [ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 b2 7f ff ff ff 7b[ 	]*vpinsrb \$0x7b,-0x81\(%rdx\),%xmm29,%xmm30
-[ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 f0 ab[ 	]*vpinsrw \$0xab,%eax,%xmm29,%xmm30
-[ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 f0 7b[ 	]*vpinsrw \$0x7b,%eax,%xmm29,%xmm30
-[ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 f5 7b[ 	]*vpinsrw \$0x7b,%ebp,%xmm29,%xmm30
-[ 	]*[a-f0-9]+:[ 	]*62 41 95 00 c4 f5 7b[ 	]*vpinsrw \$0x7b,%r13d,%xmm29,%xmm30
+[ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 f0 ab[ 	]*vpinsrw \$0xab,%rax,%xmm29,%xmm30
+[ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 f0 7b[ 	]*vpinsrw \$0x7b,%rax,%xmm29,%xmm30
+[ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 f5 7b[ 	]*vpinsrw \$0x7b,%rbp,%xmm29,%xmm30
+[ 	]*[a-f0-9]+:[ 	]*62 41 95 00 c4 f5 7b[ 	]*vpinsrw \$0x7b,%r13,%xmm29,%xmm30
 [ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 31 7b[ 	]*vpinsrw \$0x7b,\(%rcx\),%xmm29,%xmm30
 [ 	]*[a-f0-9]+:[ 	]*62 21 95 00 c4 b4 f0 23 01 00 00 7b[ 	]*vpinsrw \$0x7b,0x123\(%rax,%r14,8\),%xmm29,%xmm30
 [ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 72 7f 7b[ 	]*vpinsrw \$0x7b,0xfe\(%rdx\),%xmm29,%xmm30
@@ -708,20 +708,20 @@ Disassembly of section \.text:
 [ 	]*[a-f0-9]+:[ 	]*62 91 fd 08 c5 c6 ab[ 	]*vpextrw \$0xab,%xmm30,%rax
 [ 	]*[a-f0-9]+:[ 	]*62 91 fd 08 c5 c6 7b[ 	]*vpextrw \$0x7b,%xmm30,%rax
 [ 	]*[a-f0-9]+:[ 	]*62 11 fd 08 c5 c6 7b[ 	]*vpextrw \$0x7b,%xmm30,%r8
-[ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 f0 ab[ 	]*vpinsrb \$0xab,%eax,%xmm29,%xmm30
-[ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 f0 7b[ 	]*vpinsrb \$0x7b,%eax,%xmm29,%xmm30
-[ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 f5 7b[ 	]*vpinsrb \$0x7b,%ebp,%xmm29,%xmm30
-[ 	]*[a-f0-9]+:[ 	]*62 43 95 00 20 f5 7b[ 	]*vpinsrb \$0x7b,%r13d,%xmm29,%xmm30
+[ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 f0 ab[ 	]*vpinsrb \$0xab,%rax,%xmm29,%xmm30
+[ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 f0 7b[ 	]*vpinsrb \$0x7b,%rax,%xmm29,%xmm30
+[ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 f5 7b[ 	]*vpinsrb \$0x7b,%rbp,%xmm29,%xmm30
+[ 	]*[a-f0-9]+:[ 	]*62 43 95 00 20 f5 7b[ 	]*vpinsrb \$0x7b,%r13,%xmm29,%xmm30
 [ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 31 7b[ 	]*vpinsrb \$0x7b,\(%rcx\),%xmm29,%xmm30
 [ 	]*[a-f0-9]+:[ 	]*62 23 95 00 20 b4 f0 34 12 00 00 7b[ 	]*vpinsrb \$0x7b,0x1234\(%rax,%r14,8\),%xmm29,%xmm30
 [ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 72 7f 7b[ 	]*vpinsrb \$0x7b,0x7f\(%rdx\),%xmm29,%xmm30
 [ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 b2 80 00 00 00 7b[ 	]*vpinsrb \$0x7b,0x80\(%rdx\),%xmm29,%xmm30
 [ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 72 80 7b[ 	]*vpinsrb \$0x7b,-0x80\(%rdx\),%xmm29,%xmm30
 [ 	]*[a-f0-9]+:[ 	]*62 63 95 00 20 b2 7f ff ff ff 7b[ 	]*vpinsrb \$0x7b,-0x81\(%rdx\),%xmm29,%xmm30
-[ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 f0 ab[ 	]*vpinsrw \$0xab,%eax,%xmm29,%xmm30
-[ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 f0 7b[ 	]*vpinsrw \$0x7b,%eax,%xmm29,%xmm30
-[ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 f5 7b[ 	]*vpinsrw \$0x7b,%ebp,%xmm29,%xmm30
-[ 	]*[a-f0-9]+:[ 	]*62 41 95 00 c4 f5 7b[ 	]*vpinsrw \$0x7b,%r13d,%xmm29,%xmm30
+[ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 f0 ab[ 	]*vpinsrw \$0xab,%rax,%xmm29,%xmm30
+[ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 f0 7b[ 	]*vpinsrw \$0x7b,%rax,%xmm29,%xmm30
+[ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 f5 7b[ 	]*vpinsrw \$0x7b,%rbp,%xmm29,%xmm30
+[ 	]*[a-f0-9]+:[ 	]*62 41 95 00 c4 f5 7b[ 	]*vpinsrw \$0x7b,%r13,%xmm29,%xmm30
 [ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 31 7b[ 	]*vpinsrw \$0x7b,\(%rcx\),%xmm29,%xmm30
 [ 	]*[a-f0-9]+:[ 	]*62 21 95 00 c4 b4 f0 34 12 00 00 7b[ 	]*vpinsrw \$0x7b,0x1234\(%rax,%r14,8\),%xmm29,%xmm30
 [ 	]*[a-f0-9]+:[ 	]*62 61 95 00 c4 72 7f 7b[ 	]*vpinsrw \$0x7b,0xfe\(%rdx\),%xmm29,%xmm30
diff --git a/gas/testsuite/gas/i386/x86-64-evex-wig1-intel.d b/gas/testsuite/gas/i386/x86-64-evex-wig1-intel.d
index 240148a..f6031f2 100644
--- a/gas/testsuite/gas/i386/x86-64-evex-wig1-intel.d
+++ b/gas/testsuite/gas/i386/x86-64-evex-wig1-intel.d
@@ -23,9 +23,9 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	62 f1 fd 08 c5 c0 00 	vpextrw rax,xmm0,0x0
 [ 	]*[a-f0-9]+:	62 f3 fd 08 15 c0 00 	vpextrw rax,xmm0,0x0
 [ 	]*[a-f0-9]+:	62 f3 fd 08 15 00 00 	vpextrw WORD PTR \[rax\],xmm0,0x0
-[ 	]*[a-f0-9]+:	62 f3 fd 08 20 c0 00 	vpinsrb xmm0,xmm0,eax,0x0
+[ 	]*[a-f0-9]+:	62 f3 fd 08 20 c0 00 	vpinsrb xmm0,xmm0,rax,0x0
 [ 	]*[a-f0-9]+:	62 f3 fd 08 20 00 00 	vpinsrb xmm0,xmm0,BYTE PTR \[rax\],0x0
-[ 	]*[a-f0-9]+:	62 f1 fd 08 c4 c0 00 	vpinsrw xmm0,xmm0,eax,0x0
+[ 	]*[a-f0-9]+:	62 f1 fd 08 c4 c0 00 	vpinsrw xmm0,xmm0,rax,0x0
 [ 	]*[a-f0-9]+:	62 f1 fd 08 c4 00 00 	vpinsrw xmm0,xmm0,WORD PTR \[rax\],0x0
 [ 	]*[a-f0-9]+:	62 02 fd 4f 21 f5    	vpmovsxbd zmm30\{k7\},xmm29
 [ 	]*[a-f0-9]+:	62 02 fd cf 21 f5    	vpmovsxbd zmm30\{k7\}\{z\},xmm29
diff --git a/gas/testsuite/gas/i386/x86-64-evex-wig1.d b/gas/testsuite/gas/i386/x86-64-evex-wig1.d
index 56a937c..9c49f1c 100644
--- a/gas/testsuite/gas/i386/x86-64-evex-wig1.d
+++ b/gas/testsuite/gas/i386/x86-64-evex-wig1.d
@@ -23,9 +23,9 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	62 f1 fd 08 c5 c0 00 	vpextrw \$0x0,%xmm0,%rax
 [ 	]*[a-f0-9]+:	62 f3 fd 08 15 c0 00 	vpextrw \$0x0,%xmm0,%rax
 [ 	]*[a-f0-9]+:	62 f3 fd 08 15 00 00 	vpextrw \$0x0,%xmm0,\(%rax\)
-[ 	]*[a-f0-9]+:	62 f3 fd 08 20 c0 00 	vpinsrb \$0x0,%eax,%xmm0,%xmm0
+[ 	]*[a-f0-9]+:	62 f3 fd 08 20 c0 00 	vpinsrb \$0x0,%rax,%xmm0,%xmm0
 [ 	]*[a-f0-9]+:	62 f3 fd 08 20 00 00 	vpinsrb \$0x0,\(%rax\),%xmm0,%xmm0
-[ 	]*[a-f0-9]+:	62 f1 fd 08 c4 c0 00 	vpinsrw \$0x0,%eax,%xmm0,%xmm0
+[ 	]*[a-f0-9]+:	62 f1 fd 08 c4 c0 00 	vpinsrw \$0x0,%rax,%xmm0,%xmm0
 [ 	]*[a-f0-9]+:	62 f1 fd 08 c4 00 00 	vpinsrw \$0x0,\(%rax\),%xmm0,%xmm0
 [ 	]*[a-f0-9]+:	62 02 fd 4f 21 f5    	vpmovsxbd %xmm29,%zmm30\{%k7\}
 [ 	]*[a-f0-9]+:	62 02 fd cf 21 f5    	vpmovsxbd %xmm29,%zmm30\{%k7\}\{z\}
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 296ef26..62f8a08 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,18 @@
 2020-07-06  Jan Beulich  <jbeulich@suse.com>
 
+	* i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
+	EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
+	EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
+	EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
+	* i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
+	EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
+	EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
+	EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
+	* i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
+	entries.
+
+2020-07-06  Jan Beulich  <jbeulich@suse.com>
+
 	* i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
 	(VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
 	(prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
diff --git a/opcodes/i386-dis-evex-len.h b/opcodes/i386-dis-evex-len.h
index ce58199..51ce98f 100644
--- a/opcodes/i386-dis-evex-len.h
+++ b/opcodes/i386-dis-evex-len.h
@@ -14,6 +14,16 @@ static const struct dis386 evex_len_table[][3] = {
     { "vmovK",	{ Edq, XMScalar }, 0 },
   },
 
+  /* EVEX_LEN_0FC4_P_2 */
+  {
+    { "vpinsrw",	{ XM, Vex128, Edqw, Ib }, 0 },
+  },
+
+  /* EVEX_LEN_0FC5_P_2 */
+  {
+    { "vpextrw",	{ Gdq, XS, Ib }, 0 },
+  },
+
   /* EVEX_LEN_0FD6_P_2 */
   {
     { VEX_W_TABLE (EVEX_W_0FD6_P_2) },
@@ -173,6 +183,26 @@ static const struct dis386 evex_len_table[][3] = {
     { "vscatterpf1qpd",  { MVexVSIBQWpX }, 0 },
   },
 
+  /* EVEX_LEN_0F3A14_P_2 */
+  {
+    { "vpextrb",	{ Edqb, XM, Ib }, 0 },
+  },
+
+  /* EVEX_LEN_0F3A15_P_2 */
+  {
+    { "vpextrw",	{ Edqw, XM, Ib }, 0 },
+  },
+
+  /* EVEX_LEN_0F3A16_P_2 */
+  {
+    { "vpextrK",	{ Edq, XM, Ib }, 0 },
+  },
+
+  /* EVEX_LEN_0F3A17_P_2 */
+  {
+    { "vextractps",	{ Edqd, XMM, Ib }, 0 },
+  },
+
   /* EVEX_LEN_0F3A18_P_2_W_0 */
   {
     { Bad_Opcode },
@@ -229,6 +259,21 @@ static const struct dis386 evex_len_table[][3] = {
     { "vextractf64x4",	{ EXxmmq, XM, Ib }, 0 },
   },
 
+  /* EVEX_LEN_0F3A20_P_2 */
+  {
+    { "vpinsrb",	{ XM, Vex128, Edqb, Ib }, 0 },
+  },
+
+  /* EVEX_LEN_0F3A21_P_2_W_0 */
+  {
+    { "vinsertps",	{ XMM, Vex, EXxmm_md, Ib }, 0 },
+  },
+
+  /* EVEX_LEN_0F3A22_P_2 */
+  {
+    { "vpinsrK",	{ XM, Vex128, Edq, Ib }, 0 },
+  },
+
   /* EVEX_LEN_0F3A23_P_2_W_0 */
   {
     { Bad_Opcode },
diff --git a/opcodes/i386-dis-evex-prefix.h b/opcodes/i386-dis-evex-prefix.h
index 01998c5..f5cce6f 100644
--- a/opcodes/i386-dis-evex-prefix.h
+++ b/opcodes/i386-dis-evex-prefix.h
@@ -330,13 +330,13 @@
   {
     { Bad_Opcode },
     { Bad_Opcode },
-    { "vpinsrw",	{ XM, Vex128, Edw, Ib }, 0 },
+    { EVEX_LEN_TABLE (EVEX_LEN_0FC4_P_2) },
   },
   /* PREFIX_EVEX_0FC5 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
-    { "vpextrw",	{ Gdq, XS, Ib }, 0 },
+    { EVEX_LEN_TABLE (EVEX_LEN_0FC5_P_2) },
   },
   /* PREFIX_EVEX_0FD2 */
   {
@@ -1191,25 +1191,25 @@
   {
     { Bad_Opcode },
     { Bad_Opcode },
-    { "vpextrb",	{ Edqb, XM, Ib }, 0 },
+    { EVEX_LEN_TABLE (EVEX_LEN_0F3A14_P_2) },
   },
   /* PREFIX_EVEX_0F3A15 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
-    { "vpextrw",	{ Edqw, XM, Ib }, 0 },
+    { EVEX_LEN_TABLE (EVEX_LEN_0F3A15_P_2) },
   },
   /* PREFIX_EVEX_0F3A16 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
-    { "vpextrK",	{ Edq, XM, Ib }, 0 },
+    { EVEX_LEN_TABLE (EVEX_LEN_0F3A16_P_2) },
   },
   /* PREFIX_EVEX_0F3A17 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
-    { "vextractps",	{ Edqd, XMM, Ib }, 0 },
+    { EVEX_LEN_TABLE (EVEX_LEN_0F3A17_P_2) },
   },
   /* PREFIX_EVEX_0F3A18 */
   {
@@ -1251,7 +1251,7 @@
   {
     { Bad_Opcode },
     { Bad_Opcode },
-    { "vpinsrb",	{ XM, Vex128, Edb, Ib }, 0 },
+    { EVEX_LEN_TABLE (EVEX_LEN_0F3A20_P_2) },
   },
   /* PREFIX_EVEX_0F3A21 */
   {
@@ -1263,7 +1263,7 @@
   {
     { Bad_Opcode },
     { Bad_Opcode },
-    { "vpinsrK",	{ XM, Vex128, Edq, Ib }, 0 },
+    { EVEX_LEN_TABLE (EVEX_LEN_0F3A22_P_2) },
   },
   /* PREFIX_EVEX_0F3A23 */
   {
diff --git a/opcodes/i386-dis-evex-w.h b/opcodes/i386-dis-evex-w.h
index ed7968a..72cd648 100644
--- a/opcodes/i386-dis-evex-w.h
+++ b/opcodes/i386-dis-evex-w.h
@@ -740,7 +740,7 @@
   },
   /* EVEX_W_0F3A21_P_2 */
   {
-    { "vinsertps",	{ XMM, Vex, EXxmm_md, Ib }, 0 },
+    { EVEX_LEN_TABLE (EVEX_LEN_0F3A21_P_2_W_0) },
   },
   /* EVEX_W_0F3A23_P_2 */
   {
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 7f521b2..25a2f13 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -1830,6 +1830,8 @@ enum
   EVEX_LEN_0F6E_P_2 = 0,
   EVEX_LEN_0F7E_P_1,
   EVEX_LEN_0F7E_P_2,
+  EVEX_LEN_0FC4_P_2,
+  EVEX_LEN_0FC5_P_2,
   EVEX_LEN_0FD6_P_2,
   EVEX_LEN_0F3819_P_2_W_0,
   EVEX_LEN_0F3819_P_2_W_1,
@@ -1853,6 +1855,10 @@ enum
   EVEX_LEN_0F38C7_R_5_P_2_W_1,
   EVEX_LEN_0F38C7_R_6_P_2_W_0,
   EVEX_LEN_0F38C7_R_6_P_2_W_1,
+  EVEX_LEN_0F3A14_P_2,
+  EVEX_LEN_0F3A15_P_2,
+  EVEX_LEN_0F3A16_P_2,
+  EVEX_LEN_0F3A17_P_2,
   EVEX_LEN_0F3A18_P_2_W_0,
   EVEX_LEN_0F3A18_P_2_W_1,
   EVEX_LEN_0F3A19_P_2_W_0,
@@ -1861,6 +1867,9 @@ enum
   EVEX_LEN_0F3A1A_P_2_W_1,
   EVEX_LEN_0F3A1B_P_2_W_0,
   EVEX_LEN_0F3A1B_P_2_W_1,
+  EVEX_LEN_0F3A20_P_2,
+  EVEX_LEN_0F3A21_P_2_W_0,
+  EVEX_LEN_0F3A22_P_2,
   EVEX_LEN_0F3A23_P_2_W_0,
   EVEX_LEN_0F3A23_P_2_W_1,
   EVEX_LEN_0F3A38_P_2_W_0,