[GAS, ARM, 2/16] Add CLI extension support for Armv8.1-M Mainline

This patch implements the dsp, fp and fp.dp extensions for Armv8.1-M Mainline.

This patch also removes the fp-armv8 check from the half-precision move
instructions 'do_neon_movhf', as checking that the FP16 instructions extension
feature bit is enabled 'ARM_EXT2_FP16_INST' is enough.

gas/ChangeLog:
2019-04-15  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* config/tc-arm.c (do_neon_movhf): Remove fp-armv8 check.
	(armv8_1m_main_ext_table): New extension table.
	(arm_archs): Use the new extension table.
	* doc/c-arm.texi: Add missing arch and document new extensions.
	* testsuite/gas/arm/armv8.1-m.main-fp.d: New.
	* testsuite/gas/arm/armv8.1-m.main-fp-dp.d: New.
	* testsuite/gas/arm/armv8.1-m.main-hp.d: New.

6 files changed, 585 insertions, 4 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index bb30f84..483823c 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,13 @@
+2019-04-15  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+
+	* config/tc-arm.c (do_neon_movhf): Remove fp-armv8 check.
+	(armv8_1m_main_ext_table): New extension table.
+	(arm_archs): Use the new extension table.
+	* doc/c-arm.texi: Add missing arch and document new extensions.
+	* testsuite/gas/arm/armv8.1-m.main-fp.d: New.
+	* testsuite/gas/arm/armv8.1-m.main-fp-dp.d: New.
+	* testsuite/gas/arm/armv8.1-m.main-hp.d: New.
+
 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 
 	* config/tc-arm.c (cpu_arch_ver): Add entry for Armv8.1-M Mainline
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 4f96066..11d593c 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -16809,9 +16809,6 @@ do_neon_movhf (void)
   enum neon_shape rs = neon_select_shape (NS_HH, NS_NULL);
   constraint (rs != NS_HH, _("invalid suffix"));
 
-  constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
-	      _(BAD_FPU));
-
   if (inst.cond != COND_ALWAYS)
     {
       if (thumb_mode)
@@ -26503,6 +26500,20 @@ static const struct arm_ext_table armv8m_main_ext_table[] =
   { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
 };
 
+static const struct arm_ext_table armv8_1m_main_ext_table[] =
+{
+  ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
+		  ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP)),
+  ARM_EXT ("fp",
+	   ARM_FEATURE (0, ARM_EXT2_FP16_INST,
+			FPU_VFP_V5_SP_D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA),
+	   ALL_FP),
+  ARM_ADD ("fp.dp",
+	   ARM_FEATURE (0, ARM_EXT2_FP16_INST,
+			FPU_VFP_V5D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
 static const struct arm_ext_table armv8r_ext_table[] =
 {
   ARM_ADD ("crc", ARCH_CRC_ARMV8),
@@ -26570,7 +26581,8 @@ static const struct arm_arch_option_table arm_archs[] =
   ARM_ARCH_OPT ("armv8-m.base",	  ARM_ARCH_V8M_BASE,	FPU_ARCH_VFP),
   ARM_ARCH_OPT2 ("armv8-m.main",  ARM_ARCH_V8M_MAIN,	FPU_ARCH_VFP,
 		 armv8m_main),
-  ARM_ARCH_OPT ("armv8.1-m.main", ARM_ARCH_V8_1M_MAIN,	FPU_ARCH_VFP),
+  ARM_ARCH_OPT2 ("armv8.1-m.main", ARM_ARCH_V8_1M_MAIN,	FPU_ARCH_VFP,
+		 armv8_1m_main),
   ARM_ARCH_OPT2 ("armv8-a",	  ARM_ARCH_V8A,		FPU_ARCH_VFP, armv8a),
   ARM_ARCH_OPT2 ("armv8.1-a",	  ARM_ARCH_V8_1A,	FPU_ARCH_VFP, armv81a),
   ARM_ARCH_OPT2 ("armv8.2-a",	  ARM_ARCH_V8_2A,	FPU_ARCH_VFP, armv82a),
diff --git a/gas/doc/c-arm.texi b/gas/doc/c-arm.texi
index 184d716..4c595d8 100644
--- a/gas/doc/c-arm.texi
+++ b/gas/doc/c-arm.texi
@@ -250,6 +250,7 @@ names are recognized:
 @code{armv8.5-a},
 @code{armv8-m.base},
 @code{armv8-m.main},
+@code{armv8.1-m.main},
 @code{iwmmxt},
 @code{iwmmxt2}
 and
@@ -355,6 +356,16 @@ double-word registers.
 @code{+nofp}: Disables all FPU instructions.
 @code{+nodsp}: Disables DSP Extension.
 
+For @code{armv8.1-m.main}:
+
+@code{+dsp}: Enables DSP Extension.
+@code{+fp}: Enables single and half precision scalar Floating Point Extensions
+for Armv8.1-M Mainline with 16 double-word registers.
+@code{+fp.dp}: Enables double precision scalar Floating Point Extensions for
+Armv8.1-M Mainline, implies @code{+fp}.
+@code{+nofp}: Disables all FPU instructions.
+@code{+nodsp}: Disables DSP Extension.
+
 For @code{armv8-a}:
 
 @code{+crc}: Enables CRC32 Extension.
diff --git a/gas/testsuite/gas/arm/armv8.1-m.main-fp-dp.d b/gas/testsuite/gas/arm/armv8.1-m.main-fp-dp.d
new file mode 100644
index 0000000..79c17da
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8.1-m.main-fp-dp.d
@@ -0,0 +1,203 @@
+# name: Double precision instructions for 'armv8.1-m.main'
+# source: vfp1_t2.s
+# as: -march=armv8.1-m.main+fp.dp
+# objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0+000 <[^>]*> eeb4 0bc0 	(vcmpe\.f64|fcmped)	d0, d0
+0+004 <[^>]*> eeb5 0bc0 	(vcmpe\.f64	d0, #0.0|fcmpezd	d0)
+0+008 <[^>]*> eeb4 0b40 	(vcmp\.f64|fcmpd)	d0, d0
+0+00c <[^>]*> eeb5 0b40 	(vcmp\.f64	d0, #0.0|fcmpzd	d0)
+0+010 <[^>]*> eeb0 0bc0 	(vabs\.f64|fabsd)	d0, d0
+0+014 <[^>]*> eeb0 0b40 	(vmov\.f64|fcpyd)	d0, d0
+0+018 <[^>]*> eeb1 0b40 	(vneg\.f64|fnegd)	d0, d0
+0+01c <[^>]*> eeb1 0bc0 	(vsqrt\.f64|fsqrtd)	d0, d0
+0+020 <[^>]*> ee30 0b00 	(vadd\.f64|faddd)	d0, d0, d0
+0+024 <[^>]*> ee80 0b00 	(vdiv\.f64|fdivd)	d0, d0, d0
+0+028 <[^>]*> ee00 0b00 	(vmla\.f64|fmacd)	d0, d0, d0
+0+02c <[^>]*> ee10 0b00 	(vnmls\.f64|fmscd)	d0, d0, d0
+0+030 <[^>]*> ee20 0b00 	(vmul\.f64|fmuld)	d0, d0, d0
+0+034 <[^>]*> ee00 0b40 	(vmls\.f64|fnmacd)	d0, d0, d0
+0+038 <[^>]*> ee10 0b40 	(vnmla\.f64|fnmscd)	d0, d0, d0
+0+03c <[^>]*> ee20 0b40 	(vnmul\.f64|fnmuld)	d0, d0, d0
+0+040 <[^>]*> ee30 0b40 	(vsub\.f64|fsubd)	d0, d0, d0
+0+044 <[^>]*> ed90 0b00 	vldr	d0, \[r0\]
+0+048 <[^>]*> ed80 0b00 	vstr	d0, \[r0\]
+0+04c <[^>]*> ec90 0b02 	vldmia	r0, {d0}
+0+050 <[^>]*> ec90 0b02 	vldmia	r0, {d0}
+0+054 <[^>]*> ecb0 0b02 	vldmia	r0!, {d0}
+0+058 <[^>]*> ecb0 0b02 	vldmia	r0!, {d0}
+0+05c <[^>]*> ed30 0b02 	vldmdb	r0!, {d0}
+0+060 <[^>]*> ed30 0b02 	vldmdb	r0!, {d0}
+0+064 <[^>]*> ec80 0b02 	vstmia	r0, {d0}
+0+068 <[^>]*> ec80 0b02 	vstmia	r0, {d0}
+0+06c <[^>]*> eca0 0b02 	vstmia	r0!, {d0}
+0+070 <[^>]*> eca0 0b02 	vstmia	r0!, {d0}
+0+074 <[^>]*> ed20 0b02 	vstmdb	r0!, {d0}
+0+078 <[^>]*> ed20 0b02 	vstmdb	r0!, {d0}
+0+07c <[^>]*> eeb8 0bc0 	(vcvt\.f64\.s32|fsitod)	d0, s0
+0+080 <[^>]*> eeb8 0b40 	(vcvt\.f64\.u32|fuitod)	d0, s0
+0+084 <[^>]*> eebd 0b40 	(vcvtr\.s32\.f64|ftosid)	s0, d0
+0+088 <[^>]*> eebd 0bc0 	(vcvt\.s32\.f64|ftosizd)	s0, d0
+0+08c <[^>]*> eebc 0b40 	(vcvtr\.u32\.f64|ftouid)	s0, d0
+0+090 <[^>]*> eebc 0bc0 	(vcvt\.u32\.f64|ftouizd)	s0, d0
+0+094 <[^>]*> eeb7 0ac0 	(vcvt\.f64\.f32|fcvtds)	d0, s0
+0+098 <[^>]*> eeb7 0bc0 	(vcvt\.f32\.f64|fcvtsd)	s0, d0
+0+09c <[^>]*> ee30 0b10 	vmov\.32	r0, d0\[1\]
+0+0a0 <[^>]*> ee10 0b10 	vmov\.32	r0, d0\[0\]
+0+0a4 <[^>]*> ee20 0b10 	vmov\.32	d0\[1\], r0
+0+0a8 <[^>]*> ee00 0b10 	vmov\.32	d0\[0\], r0
+0+0ac <[^>]*> eeb5 1b40 	(vcmp\.f64	d1, #0.0|fcmpzd	d1)
+0+0b0 <[^>]*> eeb5 2b40 	(vcmp\.f64	d2, #0.0|fcmpzd	d2)
+0+0b4 <[^>]*> eeb5 fb40 	(vcmp\.f64	d15, #0.0|fcmpzd	d15)
+0+0b8 <[^>]*> eeb4 0b41 	(vcmp\.f64|fcmpd)	d0, d1
+0+0bc <[^>]*> eeb4 0b42 	(vcmp\.f64|fcmpd)	d0, d2
+0+0c0 <[^>]*> eeb4 0b4f 	(vcmp\.f64|fcmpd)	d0, d15
+0+0c4 <[^>]*> eeb4 1b40 	(vcmp\.f64|fcmpd)	d1, d0
+0+0c8 <[^>]*> eeb4 2b40 	(vcmp\.f64|fcmpd)	d2, d0
+0+0cc <[^>]*> eeb4 fb40 	(vcmp\.f64|fcmpd)	d15, d0
+0+0d0 <[^>]*> eeb4 5b4c 	(vcmp\.f64|fcmpd)	d5, d12
+0+0d4 <[^>]*> eeb1 0b41 	(vneg\.f64|fnegd)	d0, d1
+0+0d8 <[^>]*> eeb1 0b42 	(vneg\.f64|fnegd)	d0, d2
+0+0dc <[^>]*> eeb1 0b4f 	(vneg\.f64|fnegd)	d0, d15
+0+0e0 <[^>]*> eeb1 1b40 	(vneg\.f64|fnegd)	d1, d0
+0+0e4 <[^>]*> eeb1 2b40 	(vneg\.f64|fnegd)	d2, d0
+0+0e8 <[^>]*> eeb1 fb40 	(vneg\.f64|fnegd)	d15, d0
+0+0ec <[^>]*> eeb1 cb45 	(vneg\.f64|fnegd)	d12, d5
+0+0f0 <[^>]*> ee30 0b01 	(vadd\.f64|faddd)	d0, d0, d1
+0+0f4 <[^>]*> ee30 0b02 	(vadd\.f64|faddd)	d0, d0, d2
+0+0f8 <[^>]*> ee30 0b0f 	(vadd\.f64|faddd)	d0, d0, d15
+0+0fc <[^>]*> ee31 0b00 	(vadd\.f64|faddd)	d0, d1, d0
+0+100 <[^>]*> ee32 0b00 	(vadd\.f64|faddd)	d0, d2, d0
+0+104 <[^>]*> ee3f 0b00 	(vadd\.f64|faddd)	d0, d15, d0
+0+108 <[^>]*> ee30 1b00 	(vadd\.f64|faddd)	d1, d0, d0
+0+10c <[^>]*> ee30 2b00 	(vadd\.f64|faddd)	d2, d0, d0
+0+110 <[^>]*> ee30 fb00 	(vadd\.f64|faddd)	d15, d0, d0
+0+114 <[^>]*> ee39 cb05 	(vadd\.f64|faddd)	d12, d9, d5
+0+118 <[^>]*> eeb7 0ae0 	(vcvt\.f64\.f32|fcvtds)	d0, s1
+0+11c <[^>]*> eeb7 0ac1 	(vcvt\.f64\.f32|fcvtds)	d0, s2
+0+120 <[^>]*> eeb7 0aef 	(vcvt\.f64\.f32|fcvtds)	d0, s31
+0+124 <[^>]*> eeb7 1ac0 	(vcvt\.f64\.f32|fcvtds)	d1, s0
+0+128 <[^>]*> eeb7 2ac0 	(vcvt\.f64\.f32|fcvtds)	d2, s0
+0+12c <[^>]*> eeb7 fac0 	(vcvt\.f64\.f32|fcvtds)	d15, s0
+0+130 <[^>]*> eef7 0bc0 	(vcvt\.f32\.f64|fcvtsd)	s1, d0
+0+134 <[^>]*> eeb7 1bc0 	(vcvt\.f32\.f64|fcvtsd)	s2, d0
+0+138 <[^>]*> eef7 fbc0 	(vcvt\.f32\.f64|fcvtsd)	s31, d0
+0+13c <[^>]*> eeb7 0bc1 	(vcvt\.f32\.f64|fcvtsd)	s0, d1
+0+140 <[^>]*> eeb7 0bc2 	(vcvt\.f32\.f64|fcvtsd)	s0, d2
+0+144 <[^>]*> eeb7 0bcf 	(vcvt\.f32\.f64|fcvtsd)	s0, d15
+0+148 <[^>]*> ee30 1b10 	vmov\.32	r1, d0\[1\]
+0+14c <[^>]*> ee30 eb10 	vmov\.32	lr, d0\[1\]
+0+150 <[^>]*> ee31 0b10 	vmov\.32	r0, d1\[1\]
+0+154 <[^>]*> ee32 0b10 	vmov\.32	r0, d2\[1\]
+0+158 <[^>]*> ee3f 0b10 	vmov\.32	r0, d15\[1\]
+0+15c <[^>]*> ee10 1b10 	vmov\.32	r1, d0\[0\]
+0+160 <[^>]*> ee10 eb10 	vmov\.32	lr, d0\[0\]
+0+164 <[^>]*> ee11 0b10 	vmov\.32	r0, d1\[0\]
+0+168 <[^>]*> ee12 0b10 	vmov\.32	r0, d2\[0\]
+0+16c <[^>]*> ee1f 0b10 	vmov\.32	r0, d15\[0\]
+0+170 <[^>]*> ee20 1b10 	vmov\.32	d0\[1\], r1
+0+174 <[^>]*> ee20 eb10 	vmov\.32	d0\[1\], lr
+0+178 <[^>]*> ee21 0b10 	vmov\.32	d1\[1\], r0
+0+17c <[^>]*> ee22 0b10 	vmov\.32	d2\[1\], r0
+0+180 <[^>]*> ee2f 0b10 	vmov\.32	d15\[1\], r0
+0+184 <[^>]*> ee00 1b10 	vmov\.32	d0\[0\], r1
+0+188 <[^>]*> ee00 eb10 	vmov\.32	d0\[0\], lr
+0+18c <[^>]*> ee01 0b10 	vmov\.32	d1\[0\], r0
+0+190 <[^>]*> ee02 0b10 	vmov\.32	d2\[0\], r0
+0+194 <[^>]*> ee0f 0b10 	vmov\.32	d15\[0\], r0
+0+198 <[^>]*> ed91 0b00 	vldr	d0, \[r1\]
+0+19c <[^>]*> ed9e 0b00 	vldr	d0, \[lr\]
+0+1a0 <[^>]*> ed90 0b00 	vldr	d0, \[r0\]
+0+1a4 <[^>]*> ed90 0bff 	vldr	d0, \[r0, #1020\].*
+0+1a8 <[^>]*> ed10 0bff 	vldr	d0, \[r0, #-1020\].*
+0+1ac <[^>]*> ed90 1b00 	vldr	d1, \[r0\]
+0+1b0 <[^>]*> ed90 2b00 	vldr	d2, \[r0\]
+0+1b4 <[^>]*> ed90 fb00 	vldr	d15, \[r0\]
+0+1b8 <[^>]*> ed8c cbc9 	vstr	d12, \[ip, #804\].*
+0+1bc <[^>]*> ec90 1b02 	vldmia	r0, {d1}
+0+1c0 <[^>]*> ec90 2b02 	vldmia	r0, {d2}
+0+1c4 <[^>]*> ec90 fb02 	vldmia	r0, {d15}
+0+1c8 <[^>]*> ec90 0b04 	vldmia	r0, {d0-d1}
+0+1cc <[^>]*> ec90 0b06 	vldmia	r0, {d0-d2}
+0+1d0 <[^>]*> ec90 0b20 	vldmia	r0, {d0-d15}
+0+1d4 <[^>]*> ec90 1b1e 	vldmia	r0, {d1-d15}
+0+1d8 <[^>]*> ec90 2b1c 	vldmia	r0, {d2-d15}
+0+1dc <[^>]*> ec90 eb04 	vldmia	r0, {d14-d15}
+0+1e0 <[^>]*> ec91 0b02 	vldmia	r1, {d0}
+0+1e4 <[^>]*> ec9e 0b02 	vldmia	lr, {d0}
+0+1e8 <[^>]*> eeb5 0b40 	(vcmp\.f64	d0, #0.0|fcmpzd	d0)
+0+1ec <[^>]*> eeb5 1b40 	(vcmp\.f64	d1, #0.0|fcmpzd	d1)
+0+1f0 <[^>]*> eeb5 2b40 	(vcmp\.f64	d2, #0.0|fcmpzd	d2)
+0+1f4 <[^>]*> eeb5 3b40 	(vcmp\.f64	d3, #0.0|fcmpzd	d3)
+0+1f8 <[^>]*> eeb5 4b40 	(vcmp\.f64	d4, #0.0|fcmpzd	d4)
+0+1fc <[^>]*> eeb5 5b40 	(vcmp\.f64	d5, #0.0|fcmpzd	d5)
+0+200 <[^>]*> eeb5 6b40 	(vcmp\.f64	d6, #0.0|fcmpzd	d6)
+0+204 <[^>]*> eeb5 7b40 	(vcmp\.f64	d7, #0.0|fcmpzd	d7)
+0+208 <[^>]*> eeb5 8b40 	(vcmp\.f64	d8, #0.0|fcmpzd	d8)
+0+20c <[^>]*> eeb5 9b40 	(vcmp\.f64	d9, #0.0|fcmpzd	d9)
+0+210 <[^>]*> eeb5 ab40 	(vcmp\.f64	d10, #0.0|fcmpzd	d10)
+0+214 <[^>]*> eeb5 bb40 	(vcmp\.f64	d11, #0.0|fcmpzd	d11)
+0+218 <[^>]*> eeb5 cb40 	(vcmp\.f64	d12, #0.0|fcmpzd	d12)
+0+21c <[^>]*> eeb5 db40 	(vcmp\.f64	d13, #0.0|fcmpzd	d13)
+0+220 <[^>]*> eeb5 eb40 	(vcmp\.f64	d14, #0.0|fcmpzd	d14)
+0+224 <[^>]*> eeb5 fb40 	(vcmp\.f64	d15, #0.0|fcmpzd	d15)
+0+228 <[^>]*> bf01      	itttt	eq
+0+22a <[^>]*> eeb4 1bcf 	(vcmpeeq\.f64|fcmpedeq)	d1, d15
+0+22e <[^>]*> eeb5 2bc0 	(vcmpeeq\.f64	d2, #0.0|fcmpezdeq	d2)
+0+232 <[^>]*> eeb4 3b4e 	(vcmpeq\.f64|fcmpdeq)	d3, d14
+0+236 <[^>]*> eeb5 4b40 	(vcmpeq\.f64	d4, #0.0|fcmpzdeq	d4)
+0+23a <[^>]*> bf01      	itttt	eq
+0+23c <[^>]*> eeb0 5bcd 	(vabseq\.f64|fabsdeq)	d5, d13
+0+240 <[^>]*> eeb0 6b4c 	(vmoveq\.f64|fcpydeq)	d6, d12
+0+244 <[^>]*> eeb1 7b4b 	(vnegeq\.f64|fnegdeq)	d7, d11
+0+248 <[^>]*> eeb1 8bca 	(vsqrteq\.f64|fsqrtdeq)	d8, d10
+0+24c <[^>]*> bf01      	itttt	eq
+0+24e <[^>]*> ee31 9b0f 	(vaddeq\.f64|fadddeq)	d9, d1, d15
+0+252 <[^>]*> ee83 2b0e 	(vdiveq\.f64|fdivdeq)	d2, d3, d14
+0+256 <[^>]*> ee0d 4b0c 	(vmlaeq\.f64|fmacdeq)	d4, d13, d12
+0+25a <[^>]*> ee16 5b0b 	(vnmlseq\.f64|fmscdeq)	d5, d6, d11
+0+25e <[^>]*> bf01      	itttt	eq
+0+260 <[^>]*> ee2a 7b09 	(vmuleq\.f64|fmuldeq)	d7, d10, d9
+0+264 <[^>]*> ee09 8b4a 	(vmlseq\.f64|fnmacdeq)	d8, d9, d10
+0+268 <[^>]*> ee16 7b4b 	(vnmlaeq\.f64|fnmscdeq)	d7, d6, d11
+0+26c <[^>]*> ee24 5b4c 	(vnmuleq\.f64|fnmuldeq)	d5, d4, d12
+0+270 <[^>]*> bf02      	ittt	eq
+0+272 <[^>]*> ee3d 3b4e 	(vsubeq\.f64|fsubdeq)	d3, d13, d14
+0+276 <[^>]*> ed95 2b00 	vldreq	d2, \[r5\]
+0+27a <[^>]*> ed8c 1b00 	vstreq	d1, \[ip\]
+0+27e <[^>]*> bf01      	itttt	eq
+0+280 <[^>]*> ec91 1b02 	vldmiaeq	r1, {d1}
+0+284 <[^>]*> ec92 2b02 	vldmiaeq	r2, {d2}
+0+288 <[^>]*> ecb3 3b02 	vldmiaeq	r3!, {d3}
+0+28c <[^>]*> ecb4 4b02 	vldmiaeq	r4!, {d4}
+0+290 <[^>]*> bf01      	itttt	eq
+0+292 <[^>]*> ed35 5b02 	vldmdbeq	r5!, {d5}
+0+296 <[^>]*> ed36 6b02 	vldmdbeq	r6!, {d6}
+0+29a <[^>]*> ec87 fb02 	vstmiaeq	r7, {d15}
+0+29e <[^>]*> ec88 eb02 	vstmiaeq	r8, {d14}
+0+2a2 <[^>]*> bf01      	itttt	eq
+0+2a4 <[^>]*> eca9 db02 	vstmiaeq	r9!, {d13}
+0+2a8 <[^>]*> ecaa cb02 	vstmiaeq	sl!, {d12}
+0+2ac <[^>]*> ed2b bb02 	vstmdbeq	fp!, {d11}
+0+2b0 <[^>]*> ed2c ab02 	vstmdbeq	ip!, {d10}
+0+2b4 <[^>]*> bf01      	itttt	eq
+0+2b6 <[^>]*> eeb8 fbe0 	(vcvteq\.f64\.s32|fsitodeq)	d15, s1
+0+2ba <[^>]*> eeb8 1b6f 	(vcvteq\.f64\.u32|fuitodeq)	d1, s31
+0+2be <[^>]*> eefd 0b4f 	(vcvtreq\.s32\.f64|ftosideq)	s1, d15
+0+2c2 <[^>]*> eefd fbc2 	(vcvteq\.s32\.f64|ftosizdeq)	s31, d2
+0+2c6 <[^>]*> bf01      	itttt	eq
+0+2c8 <[^>]*> eefc 7b42 	(vcvtreq\.u32\.f64|ftouideq)	s15, d2
+0+2cc <[^>]*> eefc 5bc3 	(vcvteq\.u32\.f64|ftouizdeq)	s11, d3
+0+2d0 <[^>]*> eeb7 1ac5 	(vcvteq\.f64\.f32|fcvtdseq)	d1, s10
+0+2d4 <[^>]*> eef7 5bc1 	(vcvteq\.f32\.f64|fcvtsdeq)	s11, d1
+0+2d8 <[^>]*> bf01      	itttt	eq
+0+2da <[^>]*> ee31 8b10 	vmoveq\.32	r8, d1\[1\]
+0+2de <[^>]*> ee1f 7b10 	vmoveq\.32	r7, d15\[0\]
+0+2e2 <[^>]*> ee21 fb10 	vmoveq\.32	d1\[1\], pc
+0+2e6 <[^>]*> ee0f 1b10 	vmoveq\.32	d15\[0\], r1
+0+2ea <[^>]*> bf00      	nop
+0+2ec <[^>]*> bf00      	nop
+0+2ee <[^>]*> bf00      	nop
diff --git a/gas/testsuite/gas/arm/armv8.1-m.main-fp.d b/gas/testsuite/gas/arm/armv8.1-m.main-fp.d
new file mode 100644
index 0000000..dd69e0d
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8.1-m.main-fp.d
@@ -0,0 +1,270 @@
+# name: Single precision instructions for 'armv8.1-m.main'
+# source: vfp1xD_t2.s
+# as: -march=armv8.1-m.main+fp
+# objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0+000 <[^>]*> eef1 fa10 	(vmrs	APSR_nzcv, fpscr|fmstat)
+0+004 <[^>]*> eeb4 0ac0 	(vcmpe\.f32|fcmpes)	s0, s0
+0+008 <[^>]*> eeb5 0ac0 	(vcmpe\.f32	s0, #0.0|fcmpezs	s0)
+0+00c <[^>]*> eeb4 0a40 	(vcmp\.f32|fcmps)	s0, s0
+0+010 <[^>]*> eeb5 0a40 	(vcmp\.f32	s0, #0.0|fcmpzs	s0)
+0+014 <[^>]*> eeb0 0ac0 	(vabs\.f32|fabss)	s0, s0
+0+018 <[^>]*> eeb0 0a40 	(vmov\.f32|fcpys)	s0, s0
+0+01c <[^>]*> eeb1 0a40 	(vneg\.f32|fnegs)	s0, s0
+0+020 <[^>]*> eeb1 0ac0 	(vsqrt\.f32|fsqrts)	s0, s0
+0+024 <[^>]*> ee30 0a00 	(vadd\.f32|fadds)	s0, s0, s0
+0+028 <[^>]*> ee80 0a00 	(vdiv\.f32|fdivs)	s0, s0, s0
+0+02c <[^>]*> ee00 0a00 	(vmla\.f32|fmacs)	s0, s0, s0
+0+030 <[^>]*> ee10 0a00 	(vnmls\.f32|fmscs)	s0, s0, s0
+0+034 <[^>]*> ee20 0a00 	(vmul\.f32|fmuls)	s0, s0, s0
+0+038 <[^>]*> ee00 0a40 	(vmls\.f32|fnmacs)	s0, s0, s0
+0+03c <[^>]*> ee10 0a40 	(vnmla\.f32|fnmscs)	s0, s0, s0
+0+040 <[^>]*> ee20 0a40 	(vnmul\.f32|fnmuls)	s0, s0, s0
+0+044 <[^>]*> ee30 0a40 	(vsub\.f32|fsubs)	s0, s0, s0
+0+048 <[^>]*> ed90 0a00 	(vldr|flds)	s0, \[r0\]
+0+04c <[^>]*> ed80 0a00 	(vstr|fsts)	s0, \[r0\]
+0+050 <[^>]*> ec90 0a01 	(vldmia|fldmias)	r0, {s0}
+0+054 <[^>]*> ec90 0a01 	(vldmia|fldmias)	r0, {s0}
+0+058 <[^>]*> ecb0 0a01 	(vldmia|fldmias)	r0!, {s0}
+0+05c <[^>]*> ecb0 0a01 	(vldmia|fldmias)	r0!, {s0}
+0+060 <[^>]*> ed30 0a01 	(vldmdb|fldmdbs)	r0!, {s0}
+0+064 <[^>]*> ed30 0a01 	(vldmdb|fldmdbs)	r0!, {s0}
+0+068 <[^>]*> ec90 0b03 	fldmiax	r0, {d0}(	;@ Deprecated|)
+0+06c <[^>]*> ec90 0b03 	fldmiax	r0, {d0}(	;@ Deprecated|)
+0+070 <[^>]*> ecb0 0b03 	fldmiax	r0!, {d0}(	;@ Deprecated|)
+0+074 <[^>]*> ecb0 0b03 	fldmiax	r0!, {d0}(	;@ Deprecated|)
+0+078 <[^>]*> ed30 0b03 	fldmdbx	r0!, {d0}(	;@ Deprecated|)
+0+07c <[^>]*> ed30 0b03 	fldmdbx	r0!, {d0}(	;@ Deprecated|)
+0+080 <[^>]*> ec80 0a01 	(vstmia|fstmias)	r0, {s0}
+0+084 <[^>]*> ec80 0a01 	(vstmia|fstmias)	r0, {s0}
+0+088 <[^>]*> eca0 0a01 	(vstmia|fstmias)	r0!, {s0}
+0+08c <[^>]*> eca0 0a01 	(vstmia|fstmias)	r0!, {s0}
+0+090 <[^>]*> ed20 0a01 	(vstmdb|fstmdbs)	r0!, {s0}
+0+094 <[^>]*> ed20 0a01 	(vstmdb|fstmdbs)	r0!, {s0}
+0+098 <[^>]*> ec80 0b03 	fstmiax	r0, {d0}(	;@ Deprecated|)
+0+09c <[^>]*> ec80 0b03 	fstmiax	r0, {d0}(	;@ Deprecated|)
+0+0a0 <[^>]*> eca0 0b03 	fstmiax	r0!, {d0}(	;@ Deprecated|)
+0+0a4 <[^>]*> eca0 0b03 	fstmiax	r0!, {d0}(	;@ Deprecated|)
+0+0a8 <[^>]*> ed20 0b03 	fstmdbx	r0!, {d0}(	;@ Deprecated|)
+0+0ac <[^>]*> ed20 0b03 	fstmdbx	r0!, {d0}(	;@ Deprecated|)
+0+0b0 <[^>]*> eeb8 0ac0 	(vcvt\.f32\.s32|fsitos)	s0, s0
+0+0b4 <[^>]*> eeb8 0a40 	(vcvt\.f32\.u32|fuitos)	s0, s0
+0+0b8 <[^>]*> eebd 0a40 	(vcvtr\.s32\.f32|ftosis)	s0, s0
+0+0bc <[^>]*> eebd 0ac0 	(vcvt\.s32\.f32|ftosizs)	s0, s0
+0+0c0 <[^>]*> eebc 0a40 	(vcvtr\.u32\.f32|ftouis)	s0, s0
+0+0c4 <[^>]*> eebc 0ac0 	(vcvt\.u32\.f32|ftouizs)	s0, s0
+0+0c8 <[^>]*> ee10 0a10 	(vmov|fmrs)	r0, s0
+0+0cc <[^>]*> eef0 0a10 	(vmrs|fmrx)	r0, fpsid
+0+0d0 <[^>]*> eef1 0a10 	(vmrs|fmrx)	r0, fpscr
+0+0d4 <[^>]*> eef8 0a10 	(vmrs|fmrx)	r0, fpexc
+0+0d8 <[^>]*> ee00 0a10 	(vmov|fmsr)	s0, r0
+0+0dc <[^>]*> eee0 0a10 	(vmsr|fmxr)	fpsid, r0
+0+0e0 <[^>]*> eee1 0a10 	(vmsr|fmxr)	fpscr, r0
+0+0e4 <[^>]*> eee8 0a10 	(vmsr|fmxr)	fpexc, r0
+0+0e8 <[^>]*> eef5 0a40 	(vcmp\.f32	s1, #0.0|fcmpzs	s1)
+0+0ec <[^>]*> eeb5 1a40 	(vcmp\.f32	s2, #0.0|fcmpzs	s2)
+0+0f0 <[^>]*> eef5 fa40 	(vcmp\.f32	s31, #0.0|fcmpzs	s31)
+0+0f4 <[^>]*> eeb4 0a60 	(vcmp\.f32|fcmps)	s0, s1
+0+0f8 <[^>]*> eeb4 0a41 	(vcmp\.f32|fcmps)	s0, s2
+0+0fc <[^>]*> eeb4 0a6f 	(vcmp\.f32|fcmps)	s0, s31
+0+100 <[^>]*> eef4 0a40 	(vcmp\.f32|fcmps)	s1, s0
+0+104 <[^>]*> eeb4 1a40 	(vcmp\.f32|fcmps)	s2, s0
+0+108 <[^>]*> eef4 fa40 	(vcmp\.f32|fcmps)	s31, s0
+0+10c <[^>]*> eef4 aa46 	(vcmp\.f32|fcmps)	s21, s12
+0+110 <[^>]*> eeb1 0a60 	(vneg\.f32|fnegs)	s0, s1
+0+114 <[^>]*> eeb1 0a41 	(vneg\.f32|fnegs)	s0, s2
+0+118 <[^>]*> eeb1 0a6f 	(vneg\.f32|fnegs)	s0, s31
+0+11c <[^>]*> eef1 0a40 	(vneg\.f32|fnegs)	s1, s0
+0+120 <[^>]*> eeb1 1a40 	(vneg\.f32|fnegs)	s2, s0
+0+124 <[^>]*> eef1 fa40 	(vneg\.f32|fnegs)	s31, s0
+0+128 <[^>]*> eeb1 6a6a 	(vneg\.f32|fnegs)	s12, s21
+0+12c <[^>]*> ee30 0a20 	(vadd\.f32|fadds)	s0, s0, s1
+0+130 <[^>]*> ee30 0a01 	(vadd\.f32|fadds)	s0, s0, s2
+0+134 <[^>]*> ee30 0a2f 	(vadd\.f32|fadds)	s0, s0, s31
+0+138 <[^>]*> ee30 0a80 	(vadd\.f32|fadds)	s0, s1, s0
+0+13c <[^>]*> ee31 0a00 	(vadd\.f32|fadds)	s0, s2, s0
+0+140 <[^>]*> ee3f 0a80 	(vadd\.f32|fadds)	s0, s31, s0
+0+144 <[^>]*> ee70 0a00 	(vadd\.f32|fadds)	s1, s0, s0
+0+148 <[^>]*> ee30 1a00 	(vadd\.f32|fadds)	s2, s0, s0
+0+14c <[^>]*> ee70 fa00 	(vadd\.f32|fadds)	s31, s0, s0
+0+150 <[^>]*> ee3a 6aa2 	(vadd\.f32|fadds)	s12, s21, s5
+0+154 <[^>]*> eeb8 0ae0 	(vcvt\.f32\.s32|fsitos)	s0, s1
+0+158 <[^>]*> eeb8 0ac1 	(vcvt\.f32\.s32|fsitos)	s0, s2
+0+15c <[^>]*> eeb8 0aef 	(vcvt\.f32\.s32|fsitos)	s0, s31
+0+160 <[^>]*> eef8 0ac0 	(vcvt\.f32\.s32|fsitos)	s1, s0
+0+164 <[^>]*> eeb8 1ac0 	(vcvt\.f32\.s32|fsitos)	s2, s0
+0+168 <[^>]*> eef8 fac0 	(vcvt\.f32\.s32|fsitos)	s31, s0
+0+16c <[^>]*> eebd 0a60 	(vcvtr\.s32\.f32|ftosis)	s0, s1
+0+170 <[^>]*> eebd 0a41 	(vcvtr\.s32\.f32|ftosis)	s0, s2
+0+174 <[^>]*> eebd 0a6f 	(vcvtr\.s32\.f32|ftosis)	s0, s31
+0+178 <[^>]*> eefd 0a40 	(vcvtr\.s32\.f32|ftosis)	s1, s0
+0+17c <[^>]*> eebd 1a40 	(vcvtr\.s32\.f32|ftosis)	s2, s0
+0+180 <[^>]*> eefd fa40 	(vcvtr\.s32\.f32|ftosis)	s31, s0
+0+184 <[^>]*> ee00 1a10 	(vmov|fmsr)	s0, r1
+0+188 <[^>]*> ee00 7a10 	(vmov|fmsr)	s0, r7
+0+18c <[^>]*> ee00 ea10 	(vmov|fmsr)	s0, lr
+0+190 <[^>]*> ee00 0a90 	(vmov|fmsr)	s1, r0
+0+194 <[^>]*> ee01 0a10 	(vmov|fmsr)	s2, r0
+0+198 <[^>]*> ee0f 0a90 	(vmov|fmsr)	s31, r0
+0+19c <[^>]*> ee0a 7a90 	(vmov|fmsr)	s21, r7
+0+1a0 <[^>]*> eee0 1a10 	(vmsr|fmxr)	fpsid, r1
+0+1a4 <[^>]*> eee0 ea10 	(vmsr|fmxr)	fpsid, lr
+0+1a8 <[^>]*> ee10 0a90 	(vmov|fmrs)	r0, s1
+0+1ac <[^>]*> ee11 0a10 	(vmov|fmrs)	r0, s2
+0+1b0 <[^>]*> ee1f 0a90 	(vmov|fmrs)	r0, s31
+0+1b4 <[^>]*> ee10 1a10 	(vmov|fmrs)	r1, s0
+0+1b8 <[^>]*> ee10 7a10 	(vmov|fmrs)	r7, s0
+0+1bc <[^>]*> ee10 ea10 	(vmov|fmrs)	lr, s0
+0+1c0 <[^>]*> ee15 9a90 	(vmov|fmrs)	r9, s11
+0+1c4 <[^>]*> eef0 1a10 	(vmrs|fmrx)	r1, fpsid
+0+1c8 <[^>]*> eef0 ea10 	(vmrs|fmrx)	lr, fpsid
+0+1cc <[^>]*> ed91 0a00 	(vldr|flds)	s0, \[r1\]
+0+1d0 <[^>]*> ed9e 0a00 	(vldr|flds)	s0, \[lr\]
+0+1d4 <[^>]*> ed90 0a00 	(vldr|flds)	s0, \[r0\]
+0+1d8 <[^>]*> ed90 0aff 	(vldr|flds)	s0, \[r0, #1020\].*
+0+1dc <[^>]*> ed10 0aff 	(vldr|flds)	s0, \[r0, #-1020\].*
+0+1e0 <[^>]*> edd0 0a00 	(vldr|flds)	s1, \[r0\]
+0+1e4 <[^>]*> ed90 1a00 	(vldr|flds)	s2, \[r0\]
+0+1e8 <[^>]*> edd0 fa00 	(vldr|flds)	s31, \[r0\]
+0+1ec <[^>]*> edcc aac9 	(vstr|fsts)	s21, \[ip, #804\].*
+0+1f0 <[^>]*> ecd0 0a01 	(vldmia|fldmias)	r0, {s1}
+0+1f4 <[^>]*> ec90 1a01 	(vldmia|fldmias)	r0, {s2}
+0+1f8 <[^>]*> ecd0 fa01 	(vldmia|fldmias)	r0, {s31}
+0+1fc <[^>]*> ec90 0a02 	(vldmia|fldmias)	r0, {s0-s1}
+0+200 <[^>]*> ec90 0a03 	(vldmia|fldmias)	r0, {s0-s2}
+0+204 <[^>]*> ec90 0a20 	(vldmia|fldmias)	r0, {s0-s31}
+0+208 <[^>]*> ecd0 0a1f 	(vldmia|fldmias)	r0, {s1-s31}
+0+20c <[^>]*> ec90 1a1e 	(vldmia|fldmias)	r0, {s2-s31}
+0+210 <[^>]*> ec90 fa02 	(vldmia|fldmias)	r0, {s30-s31}
+0+214 <[^>]*> ec91 0a01 	(vldmia|fldmias)	r1, {s0}
+0+218 <[^>]*> ec9e 0a01 	(vldmia|fldmias)	lr, {s0}
+0+21c <[^>]*> ec80 1b03 	fstmiax	r0, {d1}(	;@ Deprecated|)
+0+220 <[^>]*> ec80 2b03 	fstmiax	r0, {d2}(	;@ Deprecated|)
+0+224 <[^>]*> ec80 fb03 	fstmiax	r0, {d15}(	;@ Deprecated|)
+0+228 <[^>]*> ec80 0b05 	fstmiax	r0, {d0-d1}(	;@ Deprecated|)
+0+22c <[^>]*> ec80 0b07 	fstmiax	r0, {d0-d2}(	;@ Deprecated|)
+0+230 <[^>]*> ec80 0b21 	fstmiax	r0, {d0-d15}(	;@ Deprecated|)
+0+234 <[^>]*> ec80 1b1f 	fstmiax	r0, {d1-d15}(	;@ Deprecated|)
+0+238 <[^>]*> ec80 2b1d 	fstmiax	r0, {d2-d15}(	;@ Deprecated|)
+0+23c <[^>]*> ec80 eb05 	fstmiax	r0, {d14-d15}(	;@ Deprecated|)
+0+240 <[^>]*> ec81 0b03 	fstmiax	r1, {d0}(	;@ Deprecated|)
+0+244 <[^>]*> ec8e 0b03 	fstmiax	lr, {d0}(	;@ Deprecated|)
+0+248 <[^>]*> eeb5 0a40 	(vcmp\.f32	s0, #0.0|fcmpzs	s0)
+0+24c <[^>]*> eef5 0a40 	(vcmp\.f32	s1, #0.0|fcmpzs	s1)
+0+250 <[^>]*> eeb5 1a40 	(vcmp\.f32	s2, #0.0|fcmpzs	s2)
+0+254 <[^>]*> eef5 1a40 	(vcmp\.f32	s3, #0.0|fcmpzs	s3)
+0+258 <[^>]*> eeb5 2a40 	(vcmp\.f32	s4, #0.0|fcmpzs	s4)
+0+25c <[^>]*> eef5 2a40 	(vcmp\.f32	s5, #0.0|fcmpzs	s5)
+0+260 <[^>]*> eeb5 3a40 	(vcmp\.f32	s6, #0.0|fcmpzs	s6)
+0+264 <[^>]*> eef5 3a40 	(vcmp\.f32	s7, #0.0|fcmpzs	s7)
+0+268 <[^>]*> eeb5 4a40 	(vcmp\.f32	s8, #0.0|fcmpzs	s8)
+0+26c <[^>]*> eef5 4a40 	(vcmp\.f32	s9, #0.0|fcmpzs	s9)
+0+270 <[^>]*> eeb5 5a40 	(vcmp\.f32	s10, #0.0|fcmpzs	s10)
+0+274 <[^>]*> eef5 5a40 	(vcmp\.f32	s11, #0.0|fcmpzs	s11)
+0+278 <[^>]*> eeb5 6a40 	(vcmp\.f32	s12, #0.0|fcmpzs	s12)
+0+27c <[^>]*> eef5 6a40 	(vcmp\.f32	s13, #0.0|fcmpzs	s13)
+0+280 <[^>]*> eeb5 7a40 	(vcmp\.f32	s14, #0.0|fcmpzs	s14)
+0+284 <[^>]*> eef5 7a40 	(vcmp\.f32	s15, #0.0|fcmpzs	s15)
+0+288 <[^>]*> eeb5 8a40 	(vcmp\.f32	s16, #0.0|fcmpzs	s16)
+0+28c <[^>]*> eef5 8a40 	(vcmp\.f32	s17, #0.0|fcmpzs	s17)
+0+290 <[^>]*> eeb5 9a40 	(vcmp\.f32	s18, #0.0|fcmpzs	s18)
+0+294 <[^>]*> eef5 9a40 	(vcmp\.f32	s19, #0.0|fcmpzs	s19)
+0+298 <[^>]*> eeb5 aa40 	(vcmp\.f32	s20, #0.0|fcmpzs	s20)
+0+29c <[^>]*> eef5 aa40 	(vcmp\.f32	s21, #0.0|fcmpzs	s21)
+0+2a0 <[^>]*> eeb5 ba40 	(vcmp\.f32	s22, #0.0|fcmpzs	s22)
+0+2a4 <[^>]*> eef5 ba40 	(vcmp\.f32	s23, #0.0|fcmpzs	s23)
+0+2a8 <[^>]*> eeb5 ca40 	(vcmp\.f32	s24, #0.0|fcmpzs	s24)
+0+2ac <[^>]*> eef5 ca40 	(vcmp\.f32	s25, #0.0|fcmpzs	s25)
+0+2b0 <[^>]*> eeb5 da40 	(vcmp\.f32	s26, #0.0|fcmpzs	s26)
+0+2b4 <[^>]*> eef5 da40 	(vcmp\.f32	s27, #0.0|fcmpzs	s27)
+0+2b8 <[^>]*> eeb5 ea40 	(vcmp\.f32	s28, #0.0|fcmpzs	s28)
+0+2bc <[^>]*> eef5 ea40 	(vcmp\.f32	s29, #0.0|fcmpzs	s29)
+0+2c0 <[^>]*> eeb5 fa40 	(vcmp\.f32	s30, #0.0|fcmpzs	s30)
+0+2c4 <[^>]*> eef5 fa40 	(vcmp\.f32	s31, #0.0|fcmpzs	s31)
+0+2c8 <[^>]*> bf01      	itttt	eq
+0+2ca <[^>]*> eef1 fa10 	(vmrseq	APSR_nzcv, fpscr|fmstateq)
+0+2ce <[^>]*> eef4 1ae3 	(vcmpeeq\.f32|fcmpeseq)	s3, s7
+0+2d2 <[^>]*> eef5 2ac0 	(vcmpeeq\.f32	s5, #0.0|fcmpezseq	s5)
+0+2d6 <[^>]*> eef4 0a41 	(vcmpeq\.f32|fcmpseq)	s1, s2
+0+2da <[^>]*> bf01      	itttt	eq
+0+2dc <[^>]*> eef5 0a40 	(vcmpeq\.f32	s1, #0.0|fcmpzseq	s1)
+0+2e0 <[^>]*> eef0 0ae1 	(vabseq\.f32|fabsseq)	s1, s3
+0+2e4 <[^>]*> eef0 fa69 	(vmoveq\.f32|fcpyseq)	s31, s19
+0+2e8 <[^>]*> eeb1 aa44 	(vnegeq\.f32|fnegseq)	s20, s8
+0+2ec <[^>]*> bf01      	itttt	eq
+0+2ee <[^>]*> eef1 2ae3 	(vsqrteq\.f32|fsqrtseq)	s5, s7
+0+2f2 <[^>]*> ee32 3a82 	(vaddeq\.f32|faddseq)	s6, s5, s4
+0+2f6 <[^>]*> eec1 1a20 	(vdiveq\.f32|fdivseq)	s3, s2, s1
+0+2fa <[^>]*> ee4f fa2e 	(vmlaeq\.f32|fmacseq)	s31, s30, s29
+0+2fe <[^>]*> bf01      	itttt	eq
+0+300 <[^>]*> ee1d ea8d 	(vnmlseq\.f32|fmscseq)	s28, s27, s26
+0+304 <[^>]*> ee6c ca2b 	(vmuleq\.f32|fmulseq)	s25, s24, s23
+0+308 <[^>]*> ee0a baca 	(vmlseq\.f32|fnmacseq)	s22, s21, s20
+0+30c <[^>]*> ee59 9a68 	(vnmlaeq\.f32|fnmscseq)	s19, s18, s17
+0+310 <[^>]*> bf01      	itttt	eq
+0+312 <[^>]*> ee27 8ac7 	(vnmuleq\.f32|fnmulseq)	s16, s15, s14
+0+316 <[^>]*> ee76 6a65 	(vsubeq\.f32|fsubseq)	s13, s12, s11
+0+31a <[^>]*> ed98 5a00 	(vldreq|fldseq)	s10, \[r8\]
+0+31e <[^>]*> edc7 4a00 	(vstreq|fstseq)	s9, \[r7\]
+0+322 <[^>]*> bf01      	itttt	eq
+0+324 <[^>]*> ec91 4a01 	(vldmiaeq|fldmiaseq)	r1, {s8}
+0+328 <[^>]*> ecd2 3a01 	(vldmiaeq|fldmiaseq)	r2, {s7}
+0+32c <[^>]*> ecb3 3a01 	(vldmiaeq|fldmiaseq)	r3!, {s6}
+0+330 <[^>]*> ecf4 2a01 	(vldmiaeq|fldmiaseq)	r4!, {s5}
+0+334 <[^>]*> bf01      	itttt	eq
+0+336 <[^>]*> ed35 2a01 	(vldmdbeq|fldmdbseq)	r5!, {s4}
+0+33a <[^>]*> ed76 1a01 	(vldmdbeq|fldmdbseq)	r6!, {s3}
+0+33e <[^>]*> ec97 1b03 	fldmiaxeq	r7, {d1}(	;@ Deprecated|)
+0+342 <[^>]*> ec98 2b03 	fldmiaxeq	r8, {d2}(	;@ Deprecated|)
+0+346 <[^>]*> bf01      	itttt	eq
+0+348 <[^>]*> ecb9 3b03 	fldmiaxeq	r9!, {d3}(	;@ Deprecated|)
+0+34c <[^>]*> ecba 4b03 	fldmiaxeq	sl!, {d4}(	;@ Deprecated|)
+0+350 <[^>]*> ed3b 5b03 	fldmdbxeq	fp!, {d5}(	;@ Deprecated|)
+0+354 <[^>]*> ed3c 6b03 	fldmdbxeq	ip!, {d6}(	;@ Deprecated|)
+0+358 <[^>]*> bf01      	itttt	eq
+0+35a <[^>]*> ec8d 1a01 	(vstmiaeq|fstmiaseq)	sp, {s2}
+0+35e <[^>]*> ecce 0a01 	(vstmiaeq|fstmiaseq)	lr, {s1}
+0+362 <[^>]*> ece1 fa01 	(vstmiaeq|fstmiaseq)	r1!, {s31}
+0+366 <[^>]*> eca2 fa01 	(vstmiaeq|fstmiaseq)	r2!, {s30}
+0+36a <[^>]*> bf01      	itttt	eq
+0+36c <[^>]*> ed63 ea01 	(vstmdbeq|fstmdbseq)	r3!, {s29}
+0+370 <[^>]*> ed24 ea01 	(vstmdbeq|fstmdbseq)	r4!, {s28}
+0+374 <[^>]*> ec85 7b03 	fstmiaxeq	r5, {d7}(	;@ Deprecated|)
+0+378 <[^>]*> ec86 8b03 	fstmiaxeq	r6, {d8}(	;@ Deprecated|)
+0+37c <[^>]*> bf01      	itttt	eq
+0+37e <[^>]*> eca7 9b03 	fstmiaxeq	r7!, {d9}(	;@ Deprecated|)
+0+382 <[^>]*> eca8 ab03 	fstmiaxeq	r8!, {d10}(	;@ Deprecated|)
+0+386 <[^>]*> ed29 bb03 	fstmdbxeq	r9!, {d11}(	;@ Deprecated|)
+0+38a <[^>]*> ed2a cb03 	fstmdbxeq	sl!, {d12}(	;@ Deprecated|)
+0+38e <[^>]*> bf01      	itttt	eq
+0+390 <[^>]*> eef8 dac3 	(vcvteq\.f32\.s32|fsitoseq)	s27, s6
+0+394 <[^>]*> eefd ca62 	(vcvtreq\.s32\.f32|ftosiseq)	s25, s5
+0+398 <[^>]*> eefd bac2 	(vcvteq\.s32\.f32|ftosizseq)	s23, s4
+0+39c <[^>]*> eefc aa61 	(vcvtreq\.u32\.f32|ftouiseq)	s21, s3
+0+3a0 <[^>]*> bf01      	itttt	eq
+0+3a2 <[^>]*> eefc 9ac1 	(vcvteq\.u32\.f32|ftouizseq)	s19, s2
+0+3a6 <[^>]*> eef8 8a60 	(vcvteq\.f32\.u32|fuitoseq)	s17, s1
+0+3aa <[^>]*> ee11 ba90 	(vmoveq|fmrseq)	fp, s3
+0+3ae <[^>]*> eef0 9a10 	(vmrseq|fmrxeq)	r9, fpsid
+0+3b2 <[^>]*> bf04      	itt	eq
+0+3b4 <[^>]*> ee01 9a90 	(vmoveq|fmsreq)	s3, r9
+0+3b8 <[^>]*> eee0 8a10 	(vmsreq|fmxreq)	fpsid, r8
+0+3bc <[^>]*> eef9 0a10 	(vmrs|fmrx)	r0, fpinst	@ Impl def
+0+3c0 <[^>]*> eefa 0a10 	(vmrs|fmrx)	r0, fpinst2	@ Impl def
+0+3c4 <[^>]*> eef7 0a10 	(vmrs|fmrx)	r0, mvfr0
+0+3c8 <[^>]*> eef6 0a10 	(vmrs|fmrx)	r0, mvfr1
+0+3cc <[^>]*> eefc 0a10 	(vmrs|fmrx)	r0, (<impl def 0xc>|vpr)
+0+3d0 <[^>]*> eee9 0a10 	(vmsr|fmxr)	fpinst, r0	@ Impl def
+0+3d4 <[^>]*> eeea 0a10 	(vmsr|fmxr)	fpinst2, r0	@ Impl def
+0+3d8 <[^>]*> eee7 0a10 	(vmsr|fmxr)	mvfr0, r0
+0+3dc <[^>]*> eee6 0a10 	(vmsr|fmxr)	mvfr1, r0
+0+3e0 <[^>]*> eeec 0a10 	(vmsr|fmxr)	(<impl def 0xc>|vpr), r0
+0+3e4 <[^>]*> bf00      	nop
+0+3e6 <[^>]*> bf00      	nop
+0+3e8 <[^>]*> bf00      	nop
+0+3ea <[^>]*> bf00      	nop
+0+3ec <[^>]*> bf00      	nop
+0+3ee <[^>]*> bf00      	nop
diff --git a/gas/testsuite/gas/arm/armv8.1-m.main-hp.d b/gas/testsuite/gas/arm/armv8.1-m.main-hp.d
new file mode 100644
index 0000000..1743d1e
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8.1-m.main-hp.d
@@ -0,0 +1,75 @@
+# name: Half precision instructions for 'armv8.1-m.main'
+# source: armv8-2-fp16-scalar.s
+# as: -march=armv8.1-m.main+fp
+# objdump: -d
+# skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd
+
+.*: +file format .*arm.*
+Disassembly of section .text:
+
+00000000 <label-0xc>:
+   0:	ee00 1910 	vmov.f16	s0, r1
+   4:	ee10 0990 	vmov.f16	r0, s1
+   8:	eeb0 0900 	vmov.f16	s0, #0	; 0x40000000  2.0
+
+0000000c <label>:
+   c:	00000ffe 	.word	0x00000ffe
+  10:	ed5f 1904 	vldr.16	s3, \[pc, #-8\]	; c <label>
+  14:	ed1f 3902 	vldr.16	s6, \[pc, #-4\]	; 14 <label\+0x8>
+  18:	eddf 1902 	vldr.16	s3, \[pc, #4\]	; 20 <label\+0x14>
+  1c:	edd0 0902 	vldr.16	s1, \[r0, #4\]
+  20:	ed10 1902 	vldr.16	s2, \[r0, #-4\]
+  24:	ed80 3902 	vstr.16	s6, \[r0, #4\]
+  28:	ed40 5902 	vstr.16	s11, \[r0, #-4\]
+  2c:	eec6 298c 	vdiv.f16	s5, s13, s24
+  30:	eee6 298c 	vfma.f16	s5, s13, s24
+  34:	eee6 29cc 	vfms.f16	s5, s13, s24
+  38:	eed6 29cc 	vfnma.f16	s5, s13, s24
+  3c:	eed6 298c 	vfnms.f16	s5, s13, s24
+  40:	fec6 298c 	vmaxnm.f16	s5, s13, s24
+  44:	fec6 29cc 	vminnm.f16	s5, s13, s24
+  48:	ee46 298c 	vmla.f16	s5, s13, s24
+  4c:	ee46 29cc 	vmls.f16	s5, s13, s24
+  50:	ee66 298c 	vmul.f16	s5, s13, s24
+  54:	ee56 29cc 	vnmla.f16	s5, s13, s24
+  58:	ee56 298c 	vnmls.f16	s5, s13, s24
+  5c:	ee66 29cc 	vnmul.f16	s5, s13, s24
+  60:	ee76 29cc 	vsub.f16	s5, s13, s24
+  64:	eef0 29c6 	vabs.f16	s5, s12
+  68:	ee72 2986 	vadd.f16	s5, s5, s12
+  6c:	eef1 29c6 	vsqrt.f16	s5, s12
+  70:	eef1 2946 	vneg.f16	s5, s12
+  74:	eeb5 1940 	vcmp.f16	s2, #0.0
+  78:	eeb5 19c0 	vcmpe.f16	s2, #0.0
+  7c:	eef4 2966 	vcmp.f16	s5, s13
+  80:	eef4 29e6 	vcmpe.f16	s5, s13
+  84:	fe46 29ab 	vseleq.f16	s5, s13, s23
+  88:	fe66 29ab 	vselge.f16	s5, s13, s23
+  8c:	fe56 29ab 	vselvs.f16	s5, s13, s23
+  90:	eefd 19c4 	vcvt.s32.f16	s3, s8
+  94:	eefc 19c4 	vcvt.u32.f16	s3, s8
+  98:	eef8 19c4 	vcvt.f16.s32	s3, s8
+  9c:	eef8 1944 	vcvt.f16.u32	s3, s8
+  a0:	eefa 39e1 	vcvt.f16.s32	s7, s7, #29
+  a4:	eefb 39e1 	vcvt.f16.u32	s7, s7, #29
+  a8:	eefe 39e1 	vcvt.s32.f16	s7, s7, #29
+  ac:	eeff 39e1 	vcvt.u32.f16	s7, s7, #29
+  b0:	fefc 29c5 	vcvta.s32.f16	s5, s10
+  b4:	fefc 2945 	vcvta.u32.f16	s5, s10
+  b8:	feff 29c5 	vcvtm.s32.f16	s5, s10
+  bc:	feff 2945 	vcvtm.u32.f16	s5, s10
+  c0:	fefd 29c5 	vcvtn.s32.f16	s5, s10
+  c4:	fefd 2945 	vcvtn.u32.f16	s5, s10
+  c8:	fefe 29c5 	vcvtp.s32.f16	s5, s10
+  cc:	fefe 2945 	vcvtp.u32.f16	s5, s10
+  d0:	eefc 2945 	vcvtr.u32.f16	s5, s10
+  d4:	eefd 2945 	vcvtr.s32.f16	s5, s10
+  d8:	fef8 1965 	vrinta.f16	s3, s11
+  dc:	fefb 1965 	vrintm.f16	s3, s11
+  e0:	fef9 1965 	vrintn.f16	s3, s11
+  e4:	fefa 1965 	vrintp.f16	s3, s11
+  e8:	eef6 1965 	vrintr.f16	s3, s11
+  ec:	eef7 1965 	vrintx.f16	s3, s11
+  f0:	eef6 19e5 	vrintz.f16	s3, s11
+  f4:	fef0 2ae4 	vins.f16	s5, s9
+  f8:	fef0 2a64 	vmovx.f16	s5, s9