opcodes: introduce BC field; fix isel

Per Power ISA Version 3.1B 3.3.12, isel uses BC field rather than CRB
field present in binutils sources. Also, per 1.6.2, BC has the same
semantics as BA and BB fields, so this should keep the same flags and
mask, only with the different offset.

opcodes/
        * ppc-opc.c
        (BC): Define new field, with the same definition as CRB field,
        but with the PPC_OPERAND_CR_BIT flag present.
gas/
        * testsuite/gas/ppc/476.d: Update.
        * testsuite/gas/ppc/a2.d: Update.
        * testsuite/gas/ppc/e500.d: Update.
        * testsuite/gas/ppc/power7.d: Update.

5 files changed, 9 insertions, 6 deletions

diff --git a/gas/testsuite/gas/ppc/476.d b/gas/testsuite/gas/ppc/476.d
index 70ea88d..e198b98 100644
--- a/gas/testsuite/gas/ppc/476.d
+++ b/gas/testsuite/gas/ppc/476.d
@@ -209,7 +209,7 @@ Disassembly of section \.text:
 .*:	(7c 20 07 8c|8c 07 20 7c) 	ici     1
 .*:	(7c 03 27 cc|cc 27 03 7c) 	icread  r3,r4
 .*:	(50 83 65 36|36 65 83 50) 	rlwimi  r3,r4,12,20,27
-.*:	(7c 43 27 1e|1e 27 43 7c) 	isel    r2,r3,r4,28
+.*:	(7c 43 27 1e|1e 27 43 7c) 	isel    r2,r3,r4,4\*cr7\+lt
 .*:	(4c 00 01 2c|2c 01 00 4c) 	isync
 .*:	(89 21 00 00|00 00 21 89) 	lbz     r9,0\(r1\)
 .*:	(8d 41 00 01|01 00 41 8d) 	lbzu    r10,1\(r1\)
diff --git a/gas/testsuite/gas/ppc/a2.d b/gas/testsuite/gas/ppc/a2.d
index f6703f4..27de396 100644
--- a/gas/testsuite/gas/ppc/a2.d
+++ b/gas/testsuite/gas/ppc/a2.d
@@ -274,7 +274,7 @@ Disassembly of section \.text:
 .*:	(7d 40 07 8c|8c 07 40 7d) 	ici     10
 .*:	(7d 4b 63 2d|2d 63 4b 7d) 	icswx\.  r10,r11,r12
 .*:	(7d 4b 63 2c|2c 63 4b 7d) 	icswx   r10,r11,r12
-.*:	(7d 4b 65 de|de 65 4b 7d) 	isel    r10,r11,r12,23
+.*:	(7d 4b 65 de|de 65 4b 7d) 	isel    r10,r11,r12,4\*cr5\+so
 .*:	(4c 00 01 2c|2c 01 00 4c) 	isync
 .*:	(7d 4b 60 be|be 60 4b 7d) 	lbepx   r10,r11,r12
 .*:	(89 4b ff ef|ef ff 4b 89) 	lbz     r10,-17\(r11\)
diff --git a/gas/testsuite/gas/ppc/e500.d b/gas/testsuite/gas/ppc/e500.d
index a7ad051..fb8a31d 100644
--- a/gas/testsuite/gas/ppc/e500.d
+++ b/gas/testsuite/gas/ppc/e500.d
@@ -7,7 +7,7 @@
 Disassembly of section \.text:
 
 0+0000000 <start>:
-   0:	(7c 43 25 de|de 25 43 7c) 	isel    r2,r3,r4,23
+   0:	(7c 43 25 de|de 25 43 7c) 	isel    r2,r3,r4,4\*cr5\+so
    4:	(7c 85 33 0c|0c 33 85 7c) 	dcblc   4,r5,r6
    8:	(7c e8 49 4c|4c 49 e8 7c) 	dcbtls  7,r8,r9
    c:	(7d 4b 61 0c|0c 61 4b 7d) 	dcbtstls 10,r11,r12
diff --git a/gas/testsuite/gas/ppc/power7.d b/gas/testsuite/gas/ppc/power7.d
index bb8d87f..3b54eb8 100644
--- a/gas/testsuite/gas/ppc/power7.d
+++ b/gas/testsuite/gas/ppc/power7.d
@@ -92,7 +92,7 @@ Disassembly of section \.text:
 .*:	(fd c0 78 35|35 78 c0 fd) 	frsqrte\. f14,f15
 .*:	(ed c0 78 34|34 78 c0 ed) 	frsqrtes f14,f15
 .*:	(ed c0 78 35|35 78 c0 ed) 	frsqrtes\. f14,f15
-.*:	(7c 43 27 1e|1e 27 43 7c) 	isel    r2,r3,r4,28
+.*:	(7c 43 27 1e|1e 27 43 7c) 	isel    r2,r3,r4,4\*cr7\+lt
 .*:	(7f 7b db 78|78 db 7b 7f) 	yield
 .*:	(7f 7b db 78|78 db 7b 7f) 	yield
 .*:	(60 42 00 00|00 00 42 60) 	ori     r2,r2,0
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index bd83d44..f5bd6da 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -2770,9 +2770,12 @@ const struct powerpc_operand powerpc_operands[] =
 #define RAB VAB + 1
   { 0x1f, 16, insert_bab, extract_bab, PPC_OPERAND_GPR },
 
+#define BC RAB + 1
+  { 0x1f, 6, NULL, NULL, PPC_OPERAND_CR_BIT },
+
   /* The BD field in a B form instruction.  The lower two bits are
      forced to zero.  */
-#define BD RAB + 1
+#define BD BC + 1
   { 0xfffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 
   /* The BD field in a B form instruction when absolute addressing is
@@ -6895,7 +6898,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"isellt",	XISEL(31,15,0),	X_MASK,	     PPCISEL,	EXT,		{RT, RA0, RB}},
 {"iselgt",	XISEL(31,15,1),	X_MASK,	     PPCISEL,	EXT,		{RT, RA0, RB}},
 {"iseleq",	XISEL(31,15,2),	X_MASK,	     PPCISEL,	EXT,		{RT, RA0, RB}},
-{"isel",	XISEL(31,15,0), XISEL_MASK, PPCISEL|TITAN, 0,		{RT, RA0, RB, CRB}},
+{"isel",	XISEL(31,15,0), XISEL_MASK, PPCISEL|TITAN, 0,		{RT, RA0, RB, BC}},
 
 {"tlbilxlpid",	XTO(31,18,0),	XTO_MASK, E500MC|PPCA2,	0,		{0}},
 {"tlbilxpid",	XTO(31,18,1),	XTO_MASK, E500MC|PPCA2,	0,		{0}},