* config/tc-mn10300.c (md_relax_table): More fixes to the offsets in this table.

  They should be correct now.
* gas/mn10300/relax.s: Add further tests of the relaxing of branch instructions.
* gas/mn10300/relax.d: Add expected relocations.

5 files changed, 109 insertions, 13 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 39bc794..8a742f6 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2004-11-23  Nick Clifton  <nickc@redhat.com>
+
+	* config/tc-mn10300.c (md_relax_table): More fixes to the offsets
+	in this table.  They should be correct now.
+
 2004-11-23 Jan Beulich <jbeulich@novell.com>
 
 	* config/tc-i386.h (CpuMMX2): Declare. Artificial classifier to
diff --git a/gas/config/tc-mn10300.c b/gas/config/tc-mn10300.c
index e2fcf75..847c974 100644
--- a/gas/config/tc-mn10300.c
+++ b/gas/config/tc-mn10300.c
@@ -54,15 +54,20 @@ const char EXP_CHARS[] = "eE";
    as in 0d1.0.  */
 const char FLT_CHARS[] = "dD";
 
-const relax_typeS md_relax_table[] = {
+const relax_typeS md_relax_table[] =
+{
+  /* The plus values for the bCC and fBCC instructions in the table below
+     are because the branch instruction is translated into a jump
+     instruction that is now +2 or +3 bytes further on in memory, and the
+     correct size of jump instruction must be selected.  */
   /* bCC relaxing  */
   {0x7f, -0x80, 2, 1},
-  {0x7fff, -0x8000 + 1, 5, 2},
+  {0x7fff + 2, -0x8000 + 2, 5, 2},
   {0x7fffffff, -0x80000000, 7, 0},
 
-  /* bCC relaxing (uncommon cases)  */
+  /* bCC relaxing (uncommon cases for 3byte length instructions)  */
   {0x7f, -0x80, 3, 4},
-  {0x7fff, -0x8000 + 1, 6, 5},
+  {0x7fff + 3, -0x8000 + 3, 6, 5},
   {0x7fffffff, -0x80000000, 8, 0},
 
   /* call relaxing  */
@@ -80,7 +85,7 @@ const relax_typeS md_relax_table[] = {
 
   /* fbCC relaxing  */
   {0x7f, -0x80, 3, 14},
-  {0x7fff, -0x8000 + 1, 6, 15},
+  {0x7fff + 3, -0x8000 + 3, 6, 15},
   {0x7fffffff, -0x80000000, 8, 0},
 
 };
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 8931766..da1423f 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2004-11-23  Nick Clifton  <nickc@redhat.com>
+
+	* gas/mn10300/relax.s: Add further tests of the relaxing of branch
+	instructions.
+	* gas/mn10300/relax.d: Add expected relocations.
+
 2004-11-22  Ravi Ramaseshan  <ravi.ramaseshan@codito.com>
 
 	* gas/arc/ld.s: Add check of load of a long immediate.
diff --git a/gas/testsuite/gas/mn10300/relax.d b/gas/testsuite/gas/mn10300/relax.d
index 069e8b6..60faa6c 100644
--- a/gas/testsuite/gas/mn10300/relax.d
+++ b/gas/testsuite/gas/mn10300/relax.d
@@ -6,12 +6,31 @@
 RELOCATION RECORDS FOR \[.rlcb\]:
 OFFSET   TYPE              VALUE 
 0+8003 R_MN10300_PCREL8  .L0._0\+0x00000001
-0+8005 R_MN10300_PCREL32  .L2\+0x00000001
+0+8005 R_MN10300_PCREL32  .L1\+0x00000001
 
-
-RELOCATION RECORDS FOR \[.rsflb\]:
+RELOCATION RECORDS FOR \[.rlfcb\]:
 OFFSET   TYPE              VALUE 
 0+8004 R_MN10300_PCREL8  .L0._1\+0x00000002
-0+8006 R_MN10300_PCREL32  .L4\+0x00000001
+0+8006 R_MN10300_PCREL32  .L2\+0x00000001
+
+RELOCATION RECORDS FOR \[.rscb\]:
+OFFSET   TYPE              VALUE 
+0+103 R_MN10300_PCREL8  .L0._2\+0x00000001
+0+105 R_MN10300_PCREL16  .L3\+0x00000001
+
+RELOCATION RECORDS FOR \[.rsfcb\]:
+OFFSET   TYPE              VALUE 
+0+104 R_MN10300_PCREL8  .L0._3\+0x00000002
+0+106 R_MN10300_PCREL16  .L4\+0x00000001
+
+RELOCATION RECORDS FOR \[.rsucb\]:
+OFFSET   TYPE              VALUE 
+0+104 R_MN10300_PCREL8  .L0._4\+0x00000002
+0+106 R_MN10300_PCREL16  .L5\+0x00000001
+
+RELOCATION RECORDS FOR \[.rlucb\]:
+OFFSET   TYPE              VALUE 
+0+8004 R_MN10300_PCREL8  .L0._5\+0x00000002
+0+8006 R_MN10300_PCREL32  .L6\+0x00000001
 
 
diff --git a/gas/testsuite/gas/mn10300/relax.s b/gas/testsuite/gas/mn10300/relax.s
index 2ef3f60..c847e97 100644
--- a/gas/testsuite/gas/mn10300/relax.s
+++ b/gas/testsuite/gas/mn10300/relax.s
@@ -5,28 +5,89 @@
 relax_long_cond_branch:
 	clr d0
 	clr d1
-.L2:
+.L1:	
 	add d1,d0
 	inc d1
 
 	.fill 32764, 1, 0xcb
 
 	cmp 9,d1
-	ble .L2
+	ble .L1
 	rets
 	
 
-	.section .rsflb, "ax"
+	.section .rlfcb, "ax"
 	.global relax_long_float_cond_branch
 relax_long_float_cond_branch:
 	clr d0
 	clr d1
-.L4:
+.L2:
 	add d1,d0
 	inc d1
 
 	.fill 32764, 1, 0xcb
 
 	cmp 9,d1
+	fble .L2
+	rets
+
+	.section .rscb, "ax"
+	.global relax_short_cond_branch
+relax_short_cond_branch:
+	clr d0
+	clr d1
+.L3:
+	add d1,d0
+	inc d1
+
+	.fill 252, 1, 0xcb
+
+	cmp 9,d1
+	ble .L3
+	rets
+
+	.section .rsfcb, "ax"
+	.global relax_short_float_cond_branch
+relax_short_float_cond_branch:
+	clr d0
+	clr d1
+.L4:
+	add d1,d0
+	inc d1
+
+	.fill 252, 1, 0xcb
+
+	cmp 9,d1
 	fble .L4
 	rets
+	
+	.section .rsucb, "ax"
+	.global relax_short_uncommon_cond_branch
+relax_short_uncommon_cond_branch:
+	clr d0
+	clr d1
+.L5:
+	add d1,d0
+	inc d1
+
+	.fill 252, 1, 0xcb
+
+	cmp 9,d1
+	bvc .L5
+	rets
+
+	.section .rlucb, "ax"
+	.global relax_long_uncommon_cond_branch
+relax_long_uncommon_cond_branch:
+	clr d0
+	clr d1
+.L6:
+	add d1,d0
+	inc d1
+
+	.fill 32764, 1, 0xcb
+
+	cmp 9,d1
+	bvc .L6
+	rets
+