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| author | Jan Beulich <jbeulich@suse.com> | 2020-01-16 10:07:05 +0100 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2020-01-16 10:07:05 +0100 |
| commit | d0849eed78268cee12d4540c67a2d9813d44f61c (patch) | |
| tree | 16361dccf0fdac02d472e38ac31177cbdb2d70f8 | |
| parent | 9cf70a448bed3f91fadc0e89ab0f4e5c0d79d975 (diff) | |
| download | gdb-d0849eed78268cee12d4540c67a2d9813d44f61c.zip gdb-d0849eed78268cee12d4540c67a2d9813d44f61c.tar.gz gdb-d0849eed78268cee12d4540c67a2d9813d44f61c.tar.bz2 | |
x86: drop stale Vec_Imm4 related comment
I overlooked this in commit 9d3bf266fd ("x86: drop Vec_Imm4"), presumably
because of the mis-spelling.
| -rw-r--r-- | opcodes/ChangeLog | 4 | ||||
| -rw-r--r-- | opcodes/i386-opc.tbl | 2 |
2 files changed, 4 insertions, 2 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index b3b51c8..eda7fa7 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,9 @@ 2020-01-16 Jan Beulich <jbeulich@suse.com> + * i386-opc.tbl: Drop stale comment from XOP section. + +2020-01-16 Jan Beulich <jbeulich@suse.com> + * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms. (extractps): Add VexWIG to SSE2AVX forms. * i386-tbl.h: Re-generate. diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index d4226fc..73cd6c6 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -2607,8 +2607,6 @@ vfnmsubss, 4, 0x667e, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=2|V vfnmsubss, 4, 0x667e, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {RegXMM, Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } // XOP instructions -// We add Imm8 to Vex_Imm4. We use Imm8 to indicate that the operand -// is an immediate. We will check if its value will fit 4 bits. vfrczpd, 2, 0x81, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } vfrczps, 2, 0x80, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } |