make vr5400 disassembly work; fix bugs in some vr5400 insns

3 files changed, 21 insertions, 11 deletions

diff --git a/opcodes/.Sanitize b/opcodes/.Sanitize
index 18961bc..730aaea 100644
--- a/opcodes/.Sanitize
+++ b/opcodes/.Sanitize
@@ -193,7 +193,7 @@ else
 	done
 fi
 
-vr5400_files="ChangeLog mips-opc.c"
+vr5400_files="ChangeLog mips-opc.c mips-dis.c"
 if ( echo $* | grep keep\-vr5400 > /dev/null ) ; then
 	for i in $vr5400_files ; do
 		if test ! -d $i && (grep sanitize-vr5400 $i > /dev/null) ; then
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index b02ce4e..6fdbf50 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,12 @@
+start-sanitize-vr5400
+Mon Nov  3 13:23:15 1997  Ken Raeburn  <raeburn@cygnus.com>
+
+	* mips-opc.c (dror32, dror, rzu.ob): Fix bugs in encoding.
+	(c.*.ob, mula.ob, mull.ob, muls.ob, mulsl.ob): Put 'k' version
+	last.
+	* mips-dis.c (print_insn_arg): Handle VR5400 operand types.
+
+end-sanitize-vr5400
 start-sanitize-tx49
 Wed Oct 29 15:10:56 1997  Gavin Koch  <gavin@cygnus.com>
 
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 60cb1ac..6a04f7c 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -393,8 +393,9 @@ const struct mips_opcode mips_builtin_opcodes[] = {
   /* start-sanitize-vr5400 */
 {"dret",    "",		0x7000003e, 0xffffffff,	0,	N5	},
 {"drorv",   "d,t,s",	0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d,	N5	},
-{"dror32",  "d,t,>",	0x0020003e, 0xffe0003f, WR_d|RD_t,	N5	},
-{"dror",    "d,t,<",	0x00200036, 0xffe0003f, WR_d|RD_t,	N5	},
+{"dror32",  "d,w,<",	0x0020003e, 0xffe0003f, WR_d|RD_t,	N5	},
+{"dror",    "d,w,>",	0x0020003e, 0xffe0003f, WR_d|RD_t,	N5	},
+{"dror",    "d,w,<",	0x00200036, 0xffe0003f, WR_d|RD_t,	N5	},
   /* end-sanitize-vr5400 */
 {"dsllv",   "d,t,s",	0x00000014, 0xfc0007ff,	WR_d|RD_t|RD_s,	I3	},
 {"dsll32",  "d,w,<",	0x0000003c, 0xffe0003f, WR_d|RD_t,	I3	},
@@ -991,15 +992,15 @@ const struct mips_opcode mips_builtin_opcodes[] = {
 {"and.ob",  "D,S,T",    0x4ac0000c, 0xffe0003f, WR_D|RD_S|RD_T,	N5	},
 {"and.ob",  "D,S,T[e]", 0x4800000c, 0xfe20003f, WR_D|RD_S|RD_T,	N5	},
 {"and.ob",  "D,S,k",    0x4bc0000c, 0xffe0003f, WR_D|RD_S|RD_T,	N5	},
-{"c.eq.ob", "S,k",	0x4bc00001, 0xffe007ff, WR_CC|RD_S|RD_T, N5	},
 {"c.eq.ob", "S,T",	0x4ac00001, 0xffe007ff, WR_CC|RD_S|RD_T, N5	},
 {"c.eq.ob", "S,T[e]",	0x48000001, 0xfe2007ff, WR_CC|RD_S|RD_T, N5	},
-{"c.le.ob", "S,k",	0x4bc00005, 0xffe007ff, WR_CC|RD_S|RD_T, N5	},
+{"c.eq.ob", "S,k",	0x4bc00001, 0xffe007ff, WR_CC|RD_S|RD_T, N5	},
 {"c.le.ob", "S,T",	0x4ac00005, 0xffe007ff, WR_CC|RD_S|RD_T, N5	},
 {"c.le.ob", "S,T[e]",	0x48000005, 0xfe2007ff, WR_CC|RD_S|RD_T, N5	},
-{"c.lt.ob", "S,k",	0x4bc00004, 0xffe007ff, WR_CC|RD_S|RD_T, N5	},
+{"c.le.ob", "S,k",	0x4bc00005, 0xffe007ff, WR_CC|RD_S|RD_T, N5	},
 {"c.lt.ob", "S,T",	0x4ac00004, 0xffe007ff, WR_CC|RD_S|RD_T, N5	},
 {"c.lt.ob", "S,T[e]",	0x48000004, 0xfe2007ff, WR_CC|RD_S|RD_T, N5	},
+{"c.lt.ob", "S,k",	0x4bc00004, 0xffe007ff, WR_CC|RD_S|RD_T, N5	},
 {"max.ob",  "D,S,T",    0x4ac00007, 0xffe0003f, WR_D|RD_S|RD_T,	N5	},
 {"max.ob",  "D,S,T[e]", 0x48000007, 0xfe20003f, WR_D|RD_S|RD_T,	N5	},
 {"max.ob",  "D,S,k",    0x4bc00007, 0xffe0003f, WR_D|RD_S|RD_T,	N5	},
@@ -1009,18 +1010,18 @@ const struct mips_opcode mips_builtin_opcodes[] = {
 {"mul.ob",  "D,S,T",    0x4ac00030, 0xffe0003f, WR_D|RD_S|RD_T,	N5	},
 {"mul.ob",  "D,S,T[e]", 0x48000030, 0xfe20003f, WR_D|RD_S|RD_T,	N5	},
 {"mul.ob",  "D,S,k",    0x4bc00030, 0xffe0003f, WR_D|RD_S|RD_T,	N5	},
-{"mula.ob", "S,k",	0x4bc00033, 0xffe007ff, WR_CC|RD_S|RD_T, N5	},
 {"mula.ob", "S,T",	0x4ac00033, 0xffe007ff, WR_CC|RD_S|RD_T, N5	},
 {"mula.ob", "S,T[e]",	0x48000033, 0xfe2007ff, WR_CC|RD_S|RD_T, N5	},
-{"mull.ob", "S,k",	0x4bc00433, 0xffe007ff, WR_CC|RD_S|RD_T, N5	},
+{"mula.ob", "S,k",	0x4bc00033, 0xffe007ff, WR_CC|RD_S|RD_T, N5	},
 {"mull.ob", "S,T",	0x4ac00433, 0xffe007ff, WR_CC|RD_S|RD_T, N5	},
 {"mull.ob", "S,T[e]",	0x48000433, 0xfe2007ff, WR_CC|RD_S|RD_T, N5	},
-{"muls.ob", "S,k",	0x4bc00032, 0xffe007ff, WR_CC|RD_S|RD_T, N5	},
+{"mull.ob", "S,k",	0x4bc00433, 0xffe007ff, WR_CC|RD_S|RD_T, N5	},
 {"muls.ob", "S,T",	0x4ac00032, 0xffe007ff, WR_CC|RD_S|RD_T, N5	},
 {"muls.ob", "S,T[e]",	0x48000032, 0xfe2007ff, WR_CC|RD_S|RD_T, N5	},
-{"mulsl.ob","S,k",	0x4bc00432, 0xffe007ff, WR_CC|RD_S|RD_T, N5	},
+{"muls.ob", "S,k",	0x4bc00032, 0xffe007ff, WR_CC|RD_S|RD_T, N5	},
 {"mulsl.ob","S,T",	0x4ac00432, 0xffe007ff, WR_CC|RD_S|RD_T, N5	},
 {"mulsl.ob","S,T[e]",	0x48000432, 0xfe2007ff, WR_CC|RD_S|RD_T, N5	},
+{"mulsl.ob","S,k",	0x4bc00432, 0xffe007ff, WR_CC|RD_S|RD_T, N5	},
 {"nor.ob",  "D,S,T",    0x4ac0000f, 0xffe0003f, WR_D|RD_S|RD_T,	N5	},
 {"nor.ob",  "D,S,T[e]", 0x4800000f, 0xfe20003f, WR_D|RD_S|RD_T,	N5	},
 {"nor.ob",  "D,S,k",    0x4bc0000f, 0xffe0003f, WR_D|RD_S|RD_T,	N5	},
@@ -1036,7 +1037,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {
 {"rach.ob", "D",	0x4a00003f, 0xfffff83f, WR_D, N5	},
 {"racl.ob", "D",	0x4800003f, 0xfffff83f, WR_D, N5	},
 {"racm.ob", "D",	0x4900003f, 0xfffff83f, WR_D, N5	},
-{"rzu.ob",  "D,S,k",    0x4bc00020, 0xffe0003f, WR_D|RD_S|RD_T,	N5	},
+{"rzu.ob",  "D,k",      0x4bc00020, 0xffe0f83f, WR_D|RD_S|RD_T,	N5	},
 {"shfl.mixh.ob","D,S,T",0x4980001f, 0xffe0003f, WR_D|RD_S|RD_T, N5	},
 {"shfl.mixl.ob","D,S,T",0x49c0001f, 0xffe0003f, WR_D|RD_S|RD_T, N5	},
 {"shfl.pach.ob","D,S,T",0x4900001f, 0xffe0003f, WR_D|RD_S|RD_T, N5	},