diff options
| author | Mike Frysinger <vapier@gentoo.org> | 2023-01-01 21:18:50 -0500 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2023-01-02 20:29:52 -0500 |
| commit | cd313814aa7b2cba1c9b5c948ead1ddb205bc2c2 (patch) | |
| tree | c22e14d7c1ee335ebb46bf2f0cc36494dc93c33a | |
| parent | 3298ee7a2c3421426729da5b3ccc25c13f623780 (diff) | |
| download | gdb-cd313814aa7b2cba1c9b5c948ead1ddb205bc2c2.zip gdb-cd313814aa7b2cba1c9b5c948ead1ddb205bc2c2.tar.gz gdb-cd313814aa7b2cba1c9b5c948ead1ddb205bc2c2.tar.bz2 | |
sim: frv: hoist cgen rules to top-level
| -rw-r--r-- | sim/Makefile.in | 10 | ||||
| -rw-r--r-- | sim/frv/Makefile.in | 24 | ||||
| -rw-r--r-- | sim/frv/local.mk | 11 |
3 files changed, 21 insertions, 24 deletions
diff --git a/sim/Makefile.in b/sim/Makefile.in index 308e8f3..9d821d3 100644 --- a/sim/Makefile.in +++ b/sim/Makefile.in @@ -3606,6 +3606,16 @@ testsuite/common/bits64m63.c: testsuite/common/bits-gen$(EXEEXT) testsuite/commo @SIM_ENABLE_ARCH_frv_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change frv/mloop.cin frv/mloop.c @SIM_ENABLE_ARCH_frv_TRUE@ $(AM_V_at)touch $@ +@SIM_ENABLE_ARCH_frv_TRUE@frv/cgen: frv/cgen-arch frv/cgen-cpu-decode + +@SIM_ENABLE_ARCH_frv_TRUE@frv/cgen-arch: +@SIM_ENABLE_ARCH_frv_TRUE@ $(AM_V_GEN)mach=all FLAGS="with-scache"; $(CGEN_GEN_ARCH) +@SIM_ENABLE_ARCH_frv_TRUE@frv/arch.h frv/arch.c frv/cpuall.h: @CGEN_MAINT@ frv/cgen-arch + +@SIM_ENABLE_ARCH_frv_TRUE@frv/cgen-cpu-decode: +@SIM_ENABLE_ARCH_frv_TRUE@ $(AM_V_GEN)cpu=frvbf mach=frv,fr550,fr500,fr450,fr400,tomcat,simple FLAGS="with-scache with-profile=fn with-generic-write with-parallel-only" EXTRAFILES="$(CGEN_CPU_SEM)"; $(CGEN_GEN_CPU_DECODE) +@SIM_ENABLE_ARCH_frv_TRUE@frv/cpu.h frv/sem.c frv/model.c frv/decode.c frv/decode.h: @CGEN_MAINT@ frv/cgen-cpu-decode + @SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/mloop.c iq2000/eng.h: iq2000/stamp-mloop ; @true @SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/stamp-mloop: $(srccom)/genmloop.sh iq2000/mloop.in @SIM_ENABLE_ARCH_iq2000_TRUE@ $(AM_V_GEN)$(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \ diff --git a/sim/frv/Makefile.in b/sim/frv/Makefile.in index 6aaf106..a137655 100644 --- a/sim/frv/Makefile.in +++ b/sim/frv/Makefile.in @@ -31,33 +31,9 @@ SIM_OBJS = \ SIM_EXTRA_CFLAGS = @SIM_FRV_TRAPDUMP_FLAGS@ -SIM_EXTRA_CLEAN = frv-clean - # Some modules don't build cleanly yet. memory.o sem.o: SIM_WERROR_CFLAGS = ## COMMON_POST_CONFIG_FRAG arch = frv - -frv-clean: - rm -f tmp-* - rm -f stamp-arch stamp-cpu - -stamp-arch: $(CGEN_READ_SCM) $(CGEN_ARCH_SCM) $(srcdir)/../../cpu/frv.cpu - $(MAKE) cgen-arch $(CGEN_FLAGS_TO_PASS) mach=all \ - archfile=$(srcdir)/../../cpu/frv.cpu \ - FLAGS="with-scache" - $(SILENCE) touch $@ -arch.h arch.c cpuall.h: $(CGEN_MAINT) stamp-arch -# @true - -stamp-cpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(srcdir)/../../cpu/frv.cpu - $(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \ - cpu=frvbf mach=frv,fr550,fr500,fr450,fr400,tomcat,simple SUFFIX= \ - archfile=$(srcdir)/../../cpu/frv.cpu \ - FLAGS="with-scache with-profile=fn with-generic-write with-parallel-only" \ - EXTRAFILES="$(CGEN_CPU_SEM)" - $(SILENCE) touch $@ -cpu.h sem.c model.c decode.c decode.h: $(CGEN_MAINT) stamp-cpu -# @true diff --git a/sim/frv/local.mk b/sim/frv/local.mk index 0dd1e3d..d5fdd1d 100644 --- a/sim/frv/local.mk +++ b/sim/frv/local.mk @@ -47,3 +47,14 @@ SIM_ALL_RECURSIVE_DEPS += $(%C%_BUILD_OUTPUTS) $(AM_V_at)touch $@ MOSTLYCLEANFILES += $(%C%_BUILD_OUTPUTS) + +## Target that triggers all cgen targets that works when --disable-cgen-maint. +%D%/cgen: %D%/cgen-arch %D%/cgen-cpu-decode + +%D%/cgen-arch: + $(AM_V_GEN)mach=all FLAGS="with-scache"; $(CGEN_GEN_ARCH) +%D%/arch.h %D%/arch.c %D%/cpuall.h: @CGEN_MAINT@ %D%/cgen-arch + +%D%/cgen-cpu-decode: + $(AM_V_GEN)cpu=frvbf mach=frv,fr550,fr500,fr450,fr400,tomcat,simple FLAGS="with-scache with-profile=fn with-generic-write with-parallel-only" EXTRAFILES="$(CGEN_CPU_SEM)"; $(CGEN_GEN_CPU_DECODE) +%D%/cpu.h %D%/sem.c %D%/model.c %D%/decode.c %D%/decode.h: @CGEN_MAINT@ %D%/cgen-cpu-decode |