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| author | Mike Frysinger <vapier@gentoo.org> | 2023-12-21 01:30:20 -0500 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2023-12-21 01:41:49 -0500 |
| commit | cc6aaa31491cacb485e07ac9adfe4f7d971b2ae2 (patch) | |
| tree | 89162c9909b6c670c7ec32f8c673c1bf11208313 | |
| parent | 3cf7f9363d4eedc3bd783c6174db872cb69c5d97 (diff) | |
| download | gdb-cc6aaa31491cacb485e07ac9adfe4f7d971b2ae2.zip gdb-cc6aaa31491cacb485e07ac9adfe4f7d971b2ae2.tar.gz gdb-cc6aaa31491cacb485e07ac9adfe4f7d971b2ae2.tar.bz2 | |
sim: cr16: add missing break statement
Doesn't seem to make sense for this to fall through
(although I'm not an expert in this ISA).
| -rw-r--r-- | sim/cr16/interp.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/sim/cr16/interp.c b/sim/cr16/interp.c index 9a2363a..0fa9a91 100644 --- a/sim/cr16/interp.c +++ b/sim/cr16/interp.c @@ -288,6 +288,7 @@ get_operands (operand_desc *s, uint64_t ins, int isize, int nops) OP[i] = (ins) & 0x3FFF; OP[++i] = (ins >> 14) & 0x1; /* get 1 bit for index-reg. */ OP[++i] = (ins >> 16) & 0xF; /* get 4 bit for reg. */ + break; case rindex7_abs20: case rindex8_abs20: OP[i] = (ins) & 0xFFFFF; |