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authorJeff Law <law@redhat.com>1997-01-16 18:28:46 +0000
committerJeff Law <law@redhat.com>1997-01-16 18:28:46 +0000
commitb4b290a02065d796b8803193deb57422b2a035c4 (patch)
tree35c534b48f2c02685accb19d5ae88310399a6f8f
parent6b01dc653b8996a9405542ee20b5292f18031a22 (diff)
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* simops.c: Fix "rol" and "ror".
Something I noticed while working on the mn10200.
-rw-r--r--sim/mn10300/ChangeLog8
-rw-r--r--sim/mn10300/simops.c4
2 files changed, 10 insertions, 2 deletions
diff --git a/sim/mn10300/ChangeLog b/sim/mn10300/ChangeLog
index e871835..8a488e6 100644
--- a/sim/mn10300/ChangeLog
+++ b/sim/mn10300/ChangeLog
@@ -1,3 +1,11 @@
+Thu Jan 16 11:28:14 1997 Jeffrey A Law (law@cygnus.com)
+
+ * simops.c: Fix "rol" and "ror".
+
+Wed Jan 15 06:45:58 1997 Jeffrey A Law (law@cygnus.com)
+
+ * simops.c: Fix typo in last change.
+
Mon Jan 13 13:22:35 1997 Jeffrey A Law (law@cygnus.com)
* simops.c: Use REG macros in few places not using them yet.
diff --git a/sim/mn10300/simops.c b/sim/mn10300/simops.c
index caa2d75..26146a1 100644
--- a/sim/mn10300/simops.c
+++ b/sim/mn10300/simops.c
@@ -2219,7 +2219,7 @@ void OP_F284 (insn, extension)
c = (value & 0x1);
value >>= 1;
- value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0;
+ value |= (c) ? 0x80000000 : 0;
State.regs[REG_D0 + REG0 (insn)] = value;
z = (value == 0);
n = (value & 0x80000000) != 0;
@@ -2238,7 +2238,7 @@ void OP_F280 (insn, extension)
c = (value & 0x80000000) ? 1 : 0;
value <<= 1;
- value |= ((PSW & PSW_C) != 0);
+ value |= c;
State.regs[REG_D0 + REG0 (insn)] = value;
z = (value == 0);
n = (value & 0x80000000) != 0;