2003-03-03 Andrew Stubbs <andrew.stubbs@superh.com>

opcodes:
	* sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
	nofpu mode.  Add BFD type bfd_mach_sh4_nommu_nofpu.
	* sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
	accordingly.
bfd:
	* archures.c: Add bfd_mach_sh4_nommu_nofpu.
	* cpu-sh.c: Ditto.
	* elf32-sh.c: Ditto.
	* bfd-in2.h: Regenerate.
include/elf:
	* sh.h: Add EF_SH4_NOMMU_NOFPU.
gas:
	* config/tc-sh.c (md_parse_option): Add -isa=sh4-nofpu and
	-isa=sh4-nommu-nofpu options. Adjust help messages accordingly.
	(sh_elf_final_processing): Output BFD type sh4_nofpu if that is
	the most general type or the user specifically requested it.
	(md_assemble): Add a new error message for when an instruction
	is understood, but is not allowed due to an -isa option.

12 files changed, 140 insertions, 36 deletions

diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index ecbeaba..83c4f41 100644
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,10 @@
+2003-03-03  Andrew Stubbs  <andrew.stubbs@superh.com>
+
+	* archures.c: Add bfd_mach_sh4_nommu_nofpu.
+	* cpu-sh.c: Ditto.
+	* elf32-sh.c: Ditto.
+	* bfd-in2.h: Regenerate.
+
 2004-03-02  Alexandre Oliva  <aoliva@redhat.com>
 
 	* elf32-frv.c (struct frv_pic_relocs_info): Added fixups and
diff --git a/bfd/archures.c b/bfd/archures.c
index 1f31b5d..0e2a08b 100644
--- a/bfd/archures.c
+++ b/bfd/archures.c
@@ -1,6 +1,6 @@
 /* BFD library support routines for architectures.
    Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
-   2000, 2001, 2002, 2003
+   2000, 2001, 2002, 2003, 2004
    Free Software Foundation, Inc.
    Hacked by John Gilmore and Steve Chamberlain of Cygnus Support.
 
@@ -230,6 +230,7 @@ DESCRIPTION
 .#define bfd_mach_sh3e       0x3e
 .#define bfd_mach_sh4        0x40
 .#define bfd_mach_sh4_nofpu  0x41
+.#define bfd_mach_sh4_nommu_nofpu  0x42
 .#define bfd_mach_sh4a       0x4a
 .#define bfd_mach_sh4a_nofpu 0x4b
 .#define bfd_mach_sh4al_dsp  0x4d
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index a56a5ee..5963bb4 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -1662,6 +1662,7 @@ enum bfd_architecture
 #define bfd_mach_sh3e       0x3e
 #define bfd_mach_sh4        0x40
 #define bfd_mach_sh4_nofpu  0x41
+#define bfd_mach_sh4_nommu_nofpu  0x42
 #define bfd_mach_sh4a       0x4a
 #define bfd_mach_sh4a_nofpu 0x4b
 #define bfd_mach_sh4al_dsp  0x4d
diff --git a/bfd/cpu-sh.c b/bfd/cpu-sh.c
index 2f33240..be359df 100644
--- a/bfd/cpu-sh.c
+++ b/bfd/cpu-sh.c
@@ -1,5 +1,5 @@
 /* BFD library support routines for the Renesas / SuperH SH architecture.
-   Copyright 1993, 1994, 1997, 1998, 2000, 2001, 2002, 2003
+   Copyright 1993, 1994, 1997, 1998, 2000, 2001, 2002, 2003, 2004
    Free Software Foundation, Inc.
    Hacked by Steve Chamberlain of Cygnus Support.
 
@@ -34,7 +34,8 @@
 #define SH4A_NEXT    &arch_info_struct[8]
 #define SH4AL_DSP_NEXT &arch_info_struct[9]
 #define SH4_NOFPU_NEXT &arch_info_struct[10]
-#define SH4A_NOFPU_NEXT &arch_info_struct[11]
+#define SH4_NOMMU_NOFPU_NEXT &arch_info_struct[11]
+#define SH4A_NOFPU_NEXT &arch_info_struct[12]
 #define SH64_NEXT    NULL
 
 static const bfd_arch_info_type arch_info_struct[] =
@@ -184,6 +185,20 @@ static const bfd_arch_info_type arch_info_struct[] =
     32,				/* 32 bits in an address */
     8,				/* 8 bits in a byte */
     bfd_arch_sh,
+    bfd_mach_sh4_nommu_nofpu,
+    "sh",			/* arch_name  */
+    "sh4-nommu-nofpu",		/* printable name */
+    1,
+    FALSE,			/* not the default */
+    bfd_default_compatible,
+    bfd_default_scan,
+    SH4_NOMMU_NOFPU_NEXT
+  },
+  {
+    32,				/* 32 bits in a word */
+    32,				/* 32 bits in an address */
+    8,				/* 8 bits in a byte */
+    bfd_arch_sh,
     bfd_mach_sh4a_nofpu,
     "sh",			/* arch_name  */
     "sh4a-nofpu",		/* printable name */
diff --git a/bfd/elf32-sh.c b/bfd/elf32-sh.c
index c8a091d..5ab56bc 100644
--- a/bfd/elf32-sh.c
+++ b/bfd/elf32-sh.c
@@ -1,5 +1,5 @@
 /* Renesas / SuperH SH specific support for 32-bit ELF
-   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004
    Free Software Foundation, Inc.
    Contributed by Ian Lance Taylor, Cygnus Support.
 
@@ -6876,6 +6876,9 @@ sh_elf_set_mach_from_flags (bfd *abfd)
     case EF_SH4AL_DSP:
       bfd_default_set_arch_mach (abfd, bfd_arch_sh, bfd_mach_sh4al_dsp);
       break;
+    case EF_SH4_NOMMU_NOFPU:
+      bfd_default_set_arch_mach (abfd, bfd_arch_sh, bfd_mach_sh4_nommu_nofpu);
+      break;
     default:
       return FALSE;
     }
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 6db536f..21acef0 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,12 @@
+2003-03-03  Andrew Stubbs  <andrew.stubbs@superh.com>
+
+	* config/tc-sh.c (md_parse_option): Add -isa=sh4-nofpu and
+	-isa=sh4-nommu-nofpu options. Adjust help messages accordingly.
+	(sh_elf_final_processing): Output BFD type sh4_nofpu if that is
+	the most general type or the user specifically requested it.
+	(md_assemble): Add a new error message for when an instruction
+	is understood, but is not allowed due to an -isa option.
+
 2004-03-02  H.J. Lu  <hongjiu.lu@intel.com>
 
 	* config/tc-ia64.c (align_frag): New.
diff --git a/gas/config/tc-sh.c b/gas/config/tc-sh.c
index ca0e38d..f3af8ab 100644
--- a/gas/config/tc-sh.c
+++ b/gas/config/tc-sh.c
@@ -2587,6 +2587,7 @@ md_assemble (char *str)
   sh_operand_info operand[3];
   sh_opcode_info *opcode;
   unsigned int size = 0;
+  char *initial_str = str;
 
 #ifdef HAVE_SH64
   if (sh64_isa_mode == sh64_isa_shmedia)
@@ -2613,7 +2614,45 @@ md_assemble (char *str)
 
   if (opcode == NULL)
     {
-      as_bad (_("unknown opcode"));
+      /* The opcode is not in the hash table.
+	 This means we definately have an assembly failure,
+	 but the instruction may be valid in another CPU variant.
+	 In this case emit something better than 'unknown opcode'.
+	 Search the full table in sh-opc.h to check. */
+
+      char *name = initial_str;
+      int name_length = 0;
+      const sh_opcode_info *op;
+      int found = 0;
+
+      /* identify opcode in string */
+      while (isspace (*name))
+	{
+	  name++;
+	}
+      while (!isspace (name[name_length]))
+	{
+	  name_length++;
+	}
+
+      /* search for opcode in full list */
+      for (op = sh_table; op->name; op++)
+	{
+	  if (strncasecmp (op->name, name, name_length) == 0)
+	    {
+	      found = 1;
+	      break;
+	    }
+	}
+
+      if ( found )
+	{
+	  as_bad (_("opcode not valid for this cpu variant"));
+	}
+      else
+	{
+	  as_bad (_("unknown opcode"));
+	}
       return;
     }
 
@@ -2895,6 +2934,10 @@ md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
     case OPTION_ISA:
       if (strcasecmp (arg, "sh4") == 0)
 	preset_target_arch = arch_sh4;
+      else if (strcasecmp (arg, "sh4-nofpu") == 0)
+	preset_target_arch = arch_sh4_nofpu;
+      else if (strcasecmp (arg, "sh4-nommu-nofpu") == 0)
+	preset_target_arch = arch_sh4_nommu_nofpu;
       else if (strcasecmp (arg, "sh4a") == 0)
 	preset_target_arch = arch_sh4a;
       else if (strcasecmp (arg, "dsp") == 0)
@@ -2976,17 +3019,20 @@ SH options:\n\
 -big			generate big endian code\n\
 -relax			alter jump instructions for long displacements\n\
 -small			align sections to 4 byte boundaries, not 16\n\
--dsp			enable sh-dsp insns, and disable floating-point ISAs.\n"));
-#ifdef HAVE_SH64
-  fprintf (stream, _("\
+-dsp			enable sh-dsp insns, and disable floating-point ISAs.\n\
 -isa=[sh4\n\
-    | sh4a\n\
-    | dsp		same as '-dsp'\n\
+    | sh4-nofpu		sh4 with fpu disabled\n\
+    | sh4-nommu-nofpu   sh4 with no MMU or FPU\n\
+    | sh4a\n\ 
+    | dsp               same as '-dsp'\n\
     | fp\n\
-    | shmedia		set as the default instruction set for SH64\n\
+    | any]		use most appropriate isa\n"));
+#ifdef HAVE_SH64
+  fprintf (stream, _("\
+-isa=[shmedia		set as the default instruction set for SH64\n\
     | SHmedia\n\
     | shcompact\n\
-    | SHcompact\n"));
+    | SHcompact]\n"));
   fprintf (stream, _("\
 -abi=[32|64]		set size of expanded SHmedia operands and object\n\
 			file type\n\
@@ -2997,13 +3043,6 @@ SH options:\n\
 -no-expand		do not expand MOVI, PT, PTA or PTB instructions\n\
 -expand-pt32		with -abi=64, expand PT, PTA and PTB instructions\n\
 			to 32 bits only\n"));
-#else
-  fprintf (stream, _("\
--isa=[sh4\n\
-    | sh4a\n\
-    | dsp		same as '-dsp'\n\
-    | fp\n\
-    | any]\n"));
 #endif /* HAVE_SH64 */
 }
 
@@ -3563,6 +3602,8 @@ sh_elf_final_processing (void)
     val = EF_SH3_DSP;
   else if (valid_arch & arch_sh3e)
     val = EF_SH3E;
+  else if (valid_arch & arch_sh4_nommu_nofpu)
+    val = EF_SH4_NOMMU_NOFPU;
   else if (valid_arch & arch_sh4_nofpu)
     val = EF_SH4_NOFPU;
   else if (valid_arch & arch_sh4)
diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog
index 707a1ab..6e4d604 100644
--- a/include/elf/ChangeLog
+++ b/include/elf/ChangeLog
@@ -1,3 +1,7 @@
+2003-03-03  Andrew Stubbs  <andrew.stubbs@superh.com>
+
+	* sh.h: Add EF_SH4_NOMMU_NOFPU.
+
 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 
 	* frv.h (EF_FRV_CPU_FR405, EF_FRV_CPU_FR450): Define.
diff --git a/include/elf/sh.h b/include/elf/sh.h
index 15d460d..c46a5ff 100644
--- a/include/elf/sh.h
+++ b/include/elf/sh.h
@@ -1,5 +1,5 @@
 /* SH ELF support for BFD.
-   Copyright 1998, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+   Copyright 1998, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
 
    This file is part of BFD, the Binary File Descriptor library.
 
@@ -39,6 +39,7 @@
 
 #define EF_SH4_NOFPU	   0x10
 #define EF_SH4A_NOFPU	   0x11
+#define EF_SH4_NOMMU_NOFPU 0x12
 
 /* This one can only mix in objects from other EF_SH5 objects.  */
 #define EF_SH5		  10
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index ba441c1..0a1498b 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,10 @@
+2003-03-03  Andrew Stubbs  <andrew.stubbs@superh.com>
+
+	* sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
+	nofpu mode.  Add BFD type bfd_mach_sh4_nommu_nofpu.
+	* sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
+	accordingly.
+
 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 
 	* frv-asm.c: Regenerate.
diff --git a/opcodes/sh-dis.c b/opcodes/sh-dis.c
index 2512f96..840823e 100644
--- a/opcodes/sh-dis.c
+++ b/opcodes/sh-dis.c
@@ -1,5 +1,5 @@
 /* Disassemble SH instructions.
-   Copyright 1993, 1994, 1995, 1997, 1998, 2000, 2001, 2002, 2003
+   Copyright 1993, 1994, 1995, 1997, 1998, 2000, 2001, 2002, 2003, 2004
    Free Software Foundation, Inc.
 
    This program is free software; you can redistribute it and/or modify
@@ -433,8 +433,10 @@ print_insn_sh (memaddr, info)
     case bfd_mach_sh3e:
       target_arch = arch_sh3e;
       break;
-    case bfd_mach_sh4:
     case bfd_mach_sh4_nofpu:
+      target_arch = arch_sh4_nofpu;
+      break;
+    case bfd_mach_sh4:
       target_arch = arch_sh4;
       break;
     case bfd_mach_sh4a:
@@ -444,6 +446,9 @@ print_insn_sh (memaddr, info)
     case bfd_mach_sh4al_dsp:
       target_arch = arch_sh4al_dsp;
       break;
+    case bfd_mach_sh4_nommu_nofpu:
+      target_arch = arch_sh4_nommu_nofpu;
+      break;
     case bfd_mach_sh5:
 #ifdef INCLUDE_SHMEDIA
       status = print_insn_sh64 (memaddr, info);
diff --git a/opcodes/sh-opc.h b/opcodes/sh-opc.h
index 0ef1fab..a1877b3 100644
--- a/opcodes/sh-opc.h
+++ b/opcodes/sh-opc.h
@@ -1,5 +1,5 @@
 /* Definitions for SH opcodes.
-   Copyright 1993, 1994, 1995, 1997, 1999, 2000, 2003
+   Copyright 1993, 1994, 1995, 1997, 1999, 2000, 2003, 2004
    Free Software Foundation, Inc.
 
    This program is free software; you can redistribute it and/or modify
@@ -188,12 +188,13 @@ sh_dsp_reg_nums;
 #define arch_sh4al_dsp 0x0400
 #define arch_sh4_nofpu 0x1000
 #define arch_sh4a_nofpu 0x2000
+#define arch_sh4_nommu_nofpu 0x4000  /* no mmu nor fpu */
 
 #define arch_sh1_up  (arch_sh1 | arch_sh2_up)
 #define arch_sh2_up  (arch_sh2 | arch_sh2e_up | arch_sh3_up | arch_sh_dsp)
 #define arch_sh2e_up (arch_sh2e | arch_sh3e_up)
 #define arch_sh3_up  (arch_sh3 | arch_sh3e_up | arch_sh3_dsp_up \
-		      | arch_sh4_nofp_up)
+		      | arch_sh4_nommu_nofpu_up)
 #define arch_sh3e_up (arch_sh3e | arch_sh4_up)
 #define arch_sh4_up  (arch_sh4 | arch_sh4a_up)
 #define arch_sh4a_up (arch_sh4a)
@@ -202,9 +203,14 @@ sh_dsp_reg_nums;
 #define arch_sh3_dsp_up (arch_sh3_dsp | arch_sh4al_dsp_up)
 #define arch_sh4al_dsp_up (arch_sh4al_dsp)
 
+#define arch_sh4_nommu_nofpu_up (arch_sh4_nommu_nofpu | arch_sh4_nofp_up)
+
 #define arch_sh4_nofp_up (arch_sh4_nofpu | arch_sh4_up | arch_sh4a_nofp_up)
 #define arch_sh4a_nofp_up (arch_sh4a_nofpu | arch_sh4a_up | arch_sh4al_dsp_up)
 
+#define arch_sh_any_with_mmu (arch_sh3 | arch_sh3e_up | arch_sh3_dsp_up \
+	| arch_sh4_nofp_up)  /* arch _sh3_up omitting arch_sh4_nommu_nofpu */
+
 typedef struct
 {
   char *name;
@@ -297,6 +303,8 @@ const sh_opcode_info sh_table[] =
 
 /* 0100nnnn00011110 ldc <REG_N>,GBR     */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh1_up},
 
+/* 0100nnnn00111010 ldc <REG_N>,SGR     */{"ldc",{A_REG_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up},
+
 /* 0100nnnn00101110 ldc <REG_N>,VBR     */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh1_up},
 
 /* 0100nnnn01011110 ldc <REG_N>,MOD     */{"ldc",{A_REG_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_E}, arch_sh_dsp_up},
@@ -309,7 +317,7 @@ const sh_opcode_info sh_table[] =
 
 /* 0100nnnn01001110 ldc <REG_N>,SPC     */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_up},
 
-/* 0100nnnn11111010 ldc <REG_N>,DBR     */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nofp_up},
+/* 0100nnnn11111010 ldc <REG_N>,DBR     */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up},
 
 /* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_up},
 
@@ -319,6 +327,8 @@ const sh_opcode_info sh_table[] =
 
 /* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh1_up},
 
+/* 0100nnnn00110110 ldc.l @<REG_N>+,SGR */{"ldc.l",{A_INC_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_6}, arch_sh4_nommu_nofpu_up},
+
 /* 0100nnnn01010111 ldc.l @<REG_N>+,MOD */{"ldc.l",{A_INC_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_7}, arch_sh_dsp_up},
 
 /* 0100nnnn01110111 ldc.l @<REG_N>+,RE */{"ldc.l",{A_INC_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_7}, arch_sh_dsp_up},
@@ -329,7 +339,7 @@ const sh_opcode_info sh_table[] =
 
 /* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_up},
 
-/* 0100nnnn11110110 ldc.l @<REG_N>+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nofp_up},
+/* 0100nnnn11110110 ldc.l @<REG_N>+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nommu_nofpu_up},
 
 /* 0100nnnn1xxx0111 ldc.l <REG_N>,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_up},
 
@@ -384,7 +394,7 @@ const sh_opcode_info sh_table[] =
   
 /* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up},
 
-/* 0000000000111000 ldtlb               */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up},
+/* 0000000000111000 ldtlb               */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh_any_with_mmu},
 
 /* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh1_up},
 
@@ -457,7 +467,7 @@ const sh_opcode_info sh_table[] =
 /* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh1_up},
 
 /* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh1_up},
-/* 0000nnnn11000011 movca.l R0,@<REG_N> */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nofp_up},
+/* 0000nnnn11000011 movca.l R0,@<REG_N> */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nommu_nofpu_up},
 
 /* 0000nnnn01110011 movco.l r0,@<REG_N> */{"movco.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_7,HEX_3}, arch_sh4a_nofp_up},
 /* 0000mmmm01100011 movli.l @<REG_M>,r0 */{"movli.l",{A_IND_M,A_R0},{HEX_0,REG_M,HEX_6,HEX_3}, arch_sh4a_nofp_up},
@@ -482,11 +492,11 @@ const sh_opcode_info sh_table[] =
 /* 0000000000001001 nop                 */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh1_up},
 
 /* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh1_up},
-/* 0000nnnn10010011 ocbi @<REG_N>       */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nofp_up},
+/* 0000nnnn10010011 ocbi @<REG_N>       */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nommu_nofpu_up},
 
-/* 0000nnnn10100011 ocbp @<REG_N>       */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nofp_up},
+/* 0000nnnn10100011 ocbp @<REG_N>       */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nommu_nofpu_up},
 
-/* 0000nnnn10110011 ocbwb @<REG_N>      */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nofp_up},
+/* 0000nnnn10110011 ocbwb @<REG_N>      */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nommu_nofpu_up},
 
 
 /* 11001011i8*1.... or #<imm>,R0        */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh1_up},
@@ -495,7 +505,7 @@ const sh_opcode_info sh_table[] =
 
 /* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh1_up},
 
-/* 0000nnnn10000011 pref @<REG_N>       */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh4_nofp_up},
+/* 0000nnnn10000011 pref @<REG_N>       */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh4_nommu_nofpu_up},
 
 /* 0000nnnn11010011 prefi @<REG_N>      */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofp_up},
 
@@ -567,9 +577,9 @@ const sh_opcode_info sh_table[] =
 
 /* 0000nnnn01000010 stc SPC,<REG_N>     */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_up},
 
-/* 0000nnnn00111010 stc SGR,<REG_N>     */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nofp_up},
+/* 0000nnnn00111010 stc SGR,<REG_N>     */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up},
 
-/* 0000nnnn11111010 stc DBR,<REG_N>     */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nofp_up},
+/* 0000nnnn11111010 stc DBR,<REG_N>     */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up},
 
 /* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_up},
 
@@ -589,9 +599,9 @@ const sh_opcode_info sh_table[] =
 
 /* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh1_up},
 
-/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nofp_up},
+/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up},
 
-/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nofp_up},
+/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up},
 
 /* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_up},