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| author | Amit Pawar <Amit.Pawar@amd.com> | 2016-11-28 09:21:05 -0800 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2016-11-28 09:21:05 -0800 |
| commit | abfcb414b9900ef996b1665323a950610dbdca43 (patch) | |
| tree | d01d715e90f3c1e8e6337cc65dd3f0cdd23f63ae | |
| parent | 1a0884415891b197972f8acf59131c3c9376807f (diff) | |
| download | gdb-abfcb414b9900ef996b1665323a950610dbdca43.zip gdb-abfcb414b9900ef996b1665323a950610dbdca43.tar.gz gdb-abfcb414b9900ef996b1665323a950610dbdca43.tar.bz2 | |
X86: Ignore REX_B bit for 32-bit XOP instructions
While decoding 32-bit XOP instructions, 64 bit registers names are printed.
This patch fixes this by ignoring REX_B bit in 32-bit mode.
opcodes/
PR binutils/20637
* i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP
instructions.
gas/
PR binutils/20637
* testsuite/gas/i386/xop32reg.d: New file.
* testsuite/gas/i386/xop32reg.s: New file.
* testsuite/gas/i386/i386.exp: Run new test.
| -rw-r--r-- | gas/ChangeLog | 8 | ||||
| -rw-r--r-- | gas/testsuite/gas/i386/i386.exp | 1 | ||||
| -rw-r--r-- | gas/testsuite/gas/i386/xop32reg.d | 15 | ||||
| -rw-r--r-- | gas/testsuite/gas/i386/xop32reg.s | 13 | ||||
| -rw-r--r-- | opcodes/ChangeLog | 7 | ||||
| -rw-r--r-- | opcodes/i386-dis.c | 12 |
6 files changed, 52 insertions, 4 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index cd0d2ab..c88a5f3 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,11 @@ +2016-11-28 Ramiro Polla <ramiro@hex-rays.com> + Amit Pawar <amit.pawar@amd.com> + + PR binutils/20637 + * testsuite/gas/i386/xop32reg.d: New file. + * testsuite/gas/i386/xop32reg.s: New file. + * testsuite/gas/i386/i386.exp: Run new test. + 2016-11-27 Ambrogino Modigliani <ambrogino.modigliani@gmail.com> * arparse.y: Fix spelling in comments. diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index 1b28fa1..29282b8 100644 --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -261,6 +261,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]] run_dump_test "fma4" run_dump_test "lwp" run_dump_test "xop" + run_dump_test "xop32reg" run_dump_test "bmi" run_dump_test "bmi-intel" run_dump_test "tbm" diff --git a/gas/testsuite/gas/i386/xop32reg.d b/gas/testsuite/gas/i386/xop32reg.d new file mode 100644 index 0000000..395bbca --- /dev/null +++ b/gas/testsuite/gas/i386/xop32reg.d @@ -0,0 +1,15 @@ +#source: xop32reg.s +#objdump: -dw +#name: i386 ignore rex_b in case of 32 bit decoding + +.*: +file format .* + + +Disassembly of section \.text: + +0+ <_start>: +[ ]*[a-f0-9]+: 8f e9 78 e1 4d c2[ ]+vphsubbw -0x3e\(%ebp\),%xmm1 +[ ]*[a-f0-9]+: 8f c9 78 e1 4d c2[ ]+vphsubbw -0x3e\(%ebp\),%xmm1 +[ ]*[a-f0-9]+: 8f e8 40 cd 04 08 07[ ]+vpcomw \$0x7,\(%eax,%ecx,1\),%xmm7,%xmm0 +[ ]*[a-f0-9]+: 8f c8 40 cd 04 08 07[ ]+vpcomw \$0x7,\(%eax,%ecx,1\),%xmm7,%xmm0 +#pass diff --git a/gas/testsuite/gas/i386/xop32reg.s b/gas/testsuite/gas/i386/xop32reg.s new file mode 100644 index 0000000..a547bd5 --- /dev/null +++ b/gas/testsuite/gas/i386/xop32reg.s @@ -0,0 +1,13 @@ + + .text +_start: + .long 0xe178e98f + .word 0xc24d + .long 0xe178c98f + .word 0xc24d + .long 0xcd40e88f + .word 0x0804 + .byte 0x07 + .long 0xcd40c88f + .word 0x0804 + .byte 0x07 diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index a839a68..9bfd67b 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,10 @@ +2016-11-28 Ramiro Polla <ramiro@hex-rays.com> + Amit Pawar <amit.pawar@amd.com> + + PR binutils/20637 + * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP + instructions. + 2016-11-22 Ambrogino Modigliani <ambrogino.modigliani@gmail.com> * configure: Regenerate. diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index 5f49f91..ada4401 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -12670,11 +12670,15 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) rex |= REX_W; vex.register_specifier = (~(*codep >> 3)) & 0xf; - if (address_mode != mode_64bit - && vex.register_specifier > 0x7) + if (address_mode != mode_64bit) { - dp = &bad_opcode; - return dp; + /* In 16/32-bit mode REX_B is silently ignored. */ + rex &= ~REX_B; + if (vex.register_specifier > 0x7) + { + dp = &bad_opcode; + return dp; + } } vex.length = (*codep & 0x4) ? 256 : 128; |