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authorPeter Bergner <bergner@vnet.ibm.com>2012-10-22 16:04:28 +0000
committerPeter Bergner <bergner@vnet.ibm.com>2012-10-22 16:04:28 +0000
commitab4437c3224faf2513c72e9361f6577e02998c5d (patch)
tree1fde67784497eaa052f30710323ce1cd4b420fef
parent08af7a403c41a1622d08134141dd9d7a2405da3e (diff)
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opcodes/
* ppc-opc.c (powerpc_opcodes) <vcfpsxws>: Fix opcode spelling. gas/testsuite/ * gas/ppc/altivec.s <vcfpsxws>: Fix opcode spelling.
-rw-r--r--gas/testsuite/ChangeLog4
-rw-r--r--gas/testsuite/gas/ppc/altivec.s2
-rw-r--r--opcodes/ChangeLog4
-rw-r--r--opcodes/ppc-opc.c2
4 files changed, 10 insertions, 2 deletions
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 0349312..b0aa64c 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2012-10-22 Peter Bergner <bergner@vnet.ibm.com>
+
+ * gas/ppc/altivec.s <vcfpsxws>: Fix opcode spelling.
+
2012-10-15 Yufeng Zhang <yufeng.zhang@arm.com>
* gas/aarch64/sysreg-1.s: Add tests of rmr_el1, rmr_el2 and rmr_el3.
diff --git a/gas/testsuite/gas/ppc/altivec.s b/gas/testsuite/gas/ppc/altivec.s
index 02af436..d5949fb 100644
--- a/gas/testsuite/gas/ppc/altivec.s
+++ b/gas/testsuite/gas/ppc/altivec.s
@@ -55,7 +55,7 @@ start:
vavgub 6,7,25
vavguh 25,22,10
vavguw 3,23,29
- vcfpsxsw 14,2,6
+ vcfpsxws 14,2,6
vcfpuxws 9,31,20
vcfsx 24,30,3
vcfux 17,21,29
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 3c57cc8..dc8f149 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2012-10-22 Peter Bergner <bergner@vnet.ibm.com>
+
+ * ppc-opc.c (powerpc_opcodes) <vcfpsxws>: Fix opcode spelling.
+
2012-10-18 Tom Tromey <tromey@redhat.com>
* tic54x-dis.c (print_instruction): Don't use K&R style.
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index cbf264b..76f5516 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -3170,7 +3170,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"maclhwsu.", XO (4, 460,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
{"vcmpbfp", VXR(4, 966,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"vctsxs", VX (4, 970), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}},
-{"vcfpsxsw", VX (4, 970), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}},
+{"vcfpsxws", VX (4, 970), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}},
{"vupklpx", VX (4, 974), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}},
{"maclhws", XO (4, 492,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
{"maclhws.", XO (4, 492,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},