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| author | Jin Ma <jinma@linux.alibaba.com> | 2023-11-18 15:04:01 +0800 |
|---|---|---|
| committer | Nelson Chu <nelson@rivosinc.com> | 2023-11-23 09:31:34 +0800 |
| commit | 9aa5dde64d7bad3f405d42ac8c25b91775864178 (patch) | |
| tree | 9792d5be280e9a9c74d848c0e57a988cb0125c6d | |
| parent | 6fdd02bb1f5bbeaa4d38b8a39e26ba414a850001 (diff) | |
| download | gdb-9aa5dde64d7bad3f405d42ac8c25b91775864178.zip gdb-9aa5dde64d7bad3f405d42ac8c25b91775864178.tar.gz gdb-9aa5dde64d7bad3f405d42ac8c25b91775864178.tar.bz2 | |
RISC-V: Add configuration-setting instructions for T-Head VECTOR vendor extension
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.
This patch adds configuration-setting instructions for the "XTheadVector"
extension. The 'th' prefix and the "XTheadVector" extension are documented
in a PR for the RISC-V toolchain conventions ([1]).
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>
gas/ChangeLog:
* testsuite/gas/riscv/x-thead-vector.d: New test.
* testsuite/gas/riscv/x-thead-vector.s: New test.
opcodes/ChangeLog:
* riscv-opc.c: Likewise..
| -rw-r--r-- | gas/testsuite/gas/riscv/x-thead-vector.d | 12 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/x-thead-vector.s | 3 | ||||
| -rw-r--r-- | opcodes/riscv-opc.c | 4 |
3 files changed, 19 insertions, 0 deletions
diff --git a/gas/testsuite/gas/riscv/x-thead-vector.d b/gas/testsuite/gas/riscv/x-thead-vector.d new file mode 100644 index 0000000..e509ed0 --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-vector.d @@ -0,0 +1,12 @@ +#as: -march=rv32if_xtheadvector +#objdump: -dr + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 <.text>: +[ ]+[0-9a-f]+:[ ]+80c5f557[ ]+th.vsetvl[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+0005f557[ ]+th.vsetvli[ ]+a0,a1,e8,m1,tu,mu +[ ]+[0-9a-f]+:[ ]+7ff5f557[ ]+th.vsetvli[ ]+a0,a1,2047 diff --git a/gas/testsuite/gas/riscv/x-thead-vector.s b/gas/testsuite/gas/riscv/x-thead-vector.s index e69de29..ffea0a6 100644 --- a/gas/testsuite/gas/riscv/x-thead-vector.s +++ b/gas/testsuite/gas/riscv/x-thead-vector.s @@ -0,0 +1,3 @@ + th.vsetvl a0, a1, a2 + th.vsetvli a0, a1, 0 + th.vsetvli a0, a1, 0x7ff diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 72d727c..4c2a9b5 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -2234,6 +2234,10 @@ const struct riscv_opcode riscv_opcodes[] = {"th.sync.is", 0, INSN_CLASS_XTHEADSYNC, "", MATCH_TH_SYNC_IS, MASK_TH_SYNC_IS, match_opcode, 0}, {"th.sync.s", 0, INSN_CLASS_XTHEADSYNC, "", MATCH_TH_SYNC_S, MASK_TH_SYNC_S, match_opcode, 0}, +/* Vendor-specific (T-Head) XTheadVector instructions. */ +{"th.vsetvl", 0, INSN_CLASS_XTHEADVECTOR, "d,s,t", MATCH_VSETVL, MASK_VSETVL, match_opcode, 0}, +{"th.vsetvli", 0, INSN_CLASS_XTHEADVECTOR, "d,s,Vc", MATCH_VSETVLI, MASK_VSETVLI, match_opcode, 0}, + /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */ {"vt.maskc", 64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 }, {"vt.maskcn", 64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKCN, MASK_VT_MASKCN, match_opcode, 0 }, |