[MIPS] Add Loongson 2K1000 proccessor support.

bfd/
	* archures.c (bfd_architecture): New machine
	bfd_mach_mips_gs264e.
	* bfd-in2.h (bfd_architecture): Likewise.
	* cpu-mips.c (enum I_xxx): Likewise.
	(arch_info_struct): Likewise.
	* elfxx-mips.c (_bfd_elf_mips_mach): Handle
	E_MIPS_MACH_GS264E.
	(mips_set_isa_flags): Likewise.
	(mips_mach_extensions): Map bfd_mach_mips_gs264e to
	bfd_mach_mips_gs464e extension.

binutils/
	* NEWS: Mention Loongson 2K1000 proccessor support.
	* readelf.c (get_machine_flags): Handle gs264e.

elfcpp/
	* mips.c (EF_MIPS_MACH): New E_MIPS_MACH_GS264E.

gas/
	* config/tc-mips.c (ISA_HAS_ODD_SINGLE_FPR): Exclude CPU_GS264E.
	(mips_cpu_info_table): Add gs264e descriptors.
	* doc/as.texi (march table): Add gs264e.

include/
	* elf/mips.h (E_MIPS_MACH_XXX): New E_MIPS_MACH_GS264E.
	* opcode/mips.h (CPU_XXX): New CPU_GS264E.

ld/
	* testsuite/ld-mips-elf/mips-elf-flags.exp: Run good_combination
	gs264e and gs464e.

opcodes/
	* mips-dis.c (mips_arch_choices): Add gs264e descriptors.

21 files changed, 83 insertions, 1 deletions

diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index 70957e1..e516b8a 100644
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,6 +1,19 @@
 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 
 	* archures.c (bfd_architecture): New machine
+	bfd_mach_mips_gs264e.
+	* bfd-in2.h (bfd_architecture): Likewise.
+	* cpu-mips.c (enum I_xxx): Likewise.
+	(arch_info_struct): Likewise.
+	* elfxx-mips.c (_bfd_elf_mips_mach): Handle
+	E_MIPS_MACH_GS264E.
+	(mips_set_isa_flags): Likewise.
+	(mips_mach_extensions): Map bfd_mach_mips_gs264e to
+	bfd_mach_mips_gs464e extension.
+
+2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
+
+	* archures.c (bfd_architecture): New machine
 	bfd_mach_mips_gs464e.
 	* bfd-in2.h (bfd_architecture): Likewise.
 	* cpu-mips.c (enum I_xxx): Likewise.
diff --git a/bfd/archures.c b/bfd/archures.c
index 2fd9bda..300e17e 100644
--- a/bfd/archures.c
+++ b/bfd/archures.c
@@ -177,6 +177,7 @@ DESCRIPTION
 .#define bfd_mach_mips_loongson_2f	3002
 .#define bfd_mach_mips_gs464		3003
 .#define bfd_mach_mips_gs464e		3004
+.#define bfd_mach_mips_gs264e		3005
 .#define bfd_mach_mips_sb1		12310201 {* octal 'SB', 01.  *}
 .#define bfd_mach_mips_octeon		6501
 .#define bfd_mach_mips_octeonp		6601
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index 6819416..1412f89 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -2071,6 +2071,7 @@ enum bfd_architecture
 #define bfd_mach_mips_loongson_2f      3002
 #define bfd_mach_mips_gs464            3003
 #define bfd_mach_mips_gs464e           3004
+#define bfd_mach_mips_gs264e           3005
 #define bfd_mach_mips_sb1              12310201 /* octal 'SB', 01.  */
 #define bfd_mach_mips_octeon           6501
 #define bfd_mach_mips_octeonp          6601
diff --git a/bfd/cpu-mips.c b/bfd/cpu-mips.c
index 2617c79..339b111 100644
--- a/bfd/cpu-mips.c
+++ b/bfd/cpu-mips.c
@@ -100,6 +100,7 @@ enum
   I_loongson_2f,
   I_gs464,
   I_gs464e,
+  I_gs264e,
   I_mipsocteon,
   I_mipsocteonp,
   I_mipsocteon2,
@@ -153,6 +154,7 @@ static const bfd_arch_info_type arch_info_struct[] =
   N (64, 64, bfd_mach_mips_loongson_2f, "mips:loongson_2f",	  FALSE, NN(I_loongson_2f)),
   N (64, 64, bfd_mach_mips_gs464, "mips:gs464",	  FALSE, NN(I_gs464)),
   N (64, 64, bfd_mach_mips_gs464e, "mips:gs464e",	  FALSE, NN(I_gs464e)),
+  N (64, 64, bfd_mach_mips_gs264e, "mips:gs264e",	  FALSE, NN(I_gs264e)),
   N (64, 64, bfd_mach_mips_octeon,"mips:octeon",  FALSE, NN(I_mipsocteon)),
   N (64, 64, bfd_mach_mips_octeonp,"mips:octeon+",  FALSE, NN(I_mipsocteonp)),
   N (64, 64, bfd_mach_mips_octeon2,"mips:octeon2",  FALSE, NN(I_mipsocteon2)),
diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c
index 25c2d9c..14621cd 100644
--- a/bfd/elfxx-mips.c
+++ b/bfd/elfxx-mips.c
@@ -6793,6 +6793,9 @@ _bfd_elf_mips_mach (flagword flags)
     case E_MIPS_MACH_GS464E:
       return bfd_mach_mips_gs464e;
 
+    case E_MIPS_MACH_GS264E:
+      return bfd_mach_mips_gs264e;
+
     case E_MIPS_MACH_OCTEON3:
       return bfd_mach_mips_octeon3;
 
@@ -11995,6 +11998,10 @@ mips_set_isa_flags (bfd *abfd)
       val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_GS464E;
       break;
 
+    case bfd_mach_mips_gs264e:
+      val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_GS264E;
+      break;
+
     case bfd_mach_mips_octeon:
     case bfd_mach_mips_octeonp:
       val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_OCTEON;
@@ -14000,6 +14007,7 @@ static const struct mips_mach_extension mips_mach_extensions[] =
   { bfd_mach_mips_octeon2, bfd_mach_mips_octeonp },
   { bfd_mach_mips_octeonp, bfd_mach_mips_octeon },
   { bfd_mach_mips_octeon, bfd_mach_mipsisa64r2 },
+  { bfd_mach_mips_gs264e, bfd_mach_mips_gs464e },
   { bfd_mach_mips_gs464e, bfd_mach_mips_gs464 },
   { bfd_mach_mips_gs464, bfd_mach_mipsisa64r2 },
 
diff --git a/binutils/ChangeLog b/binutils/ChangeLog
index ed5760e..cfc0c27 100644
--- a/binutils/ChangeLog
+++ b/binutils/ChangeLog
@@ -1,5 +1,10 @@
 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 
+	* NEWS: Mention Loongson 2K1000 proccessor support.
+	* readelf.c (get_machine_flags): Handle gs264e.
+
+2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
+
 	* NEWS: Mention Loongson 3A2000/3A3000 proccessor support.
 	* readelf.c (get_machine_flags): Handle gs464e.
 
diff --git a/binutils/NEWS b/binutils/NEWS
index 775436d..de70c3a 100644
--- a/binutils/NEWS
+++ b/binutils/NEWS
@@ -1,5 +1,10 @@
 -*- text -*-
 
+* The MIPS port now supports the Loongson 2K1000 processor which implements
+  the MIPS64r2 ISA, the Loongson-mmi ASE, Loongson-cam ASE, Loongson-ext ASE,
+  Loongson-ext2 ASE and MSA ASE instructions. Add -march=gs264e option for
+  Loongson 2K1000 processor.
+
 * The MIPS port now supports the Loongson 3A2000/3A3000 processor which
   implements the MIPS64r2 ISA, the Loongson-mmi ASE, Loongson-cam ASE,
   Loongson-ext ASE and Loongson-ext2 ASE instructions. Add -march=gs464e
diff --git a/binutils/readelf.c b/binutils/readelf.c
index 16f759e..194f1c3 100644
--- a/binutils/readelf.c
+++ b/binutils/readelf.c
@@ -3406,6 +3406,7 @@ get_machine_flags (Filedata * filedata, unsigned e_flags, unsigned e_machine)
   	    case E_MIPS_MACH_LS2F: strcat (buf, ", loongson-2f"); break;
 	    case E_MIPS_MACH_GS464: strcat (buf, ", gs464"); break;
 	    case E_MIPS_MACH_GS464E: strcat (buf, ", gs464e"); break;
+	    case E_MIPS_MACH_GS264E: strcat (buf, ", gs264e"); break;
 	    case E_MIPS_MACH_OCTEON: strcat (buf, ", octeon"); break;
 	    case E_MIPS_MACH_OCTEON2: strcat (buf, ", octeon2"); break;
 	    case E_MIPS_MACH_OCTEON3: strcat (buf, ", octeon3"); break;
diff --git a/elfcpp/ChangeLog b/elfcpp/ChangeLog
index c744299..ecae362 100644
--- a/elfcpp/ChangeLog
+++ b/elfcpp/ChangeLog
@@ -1,5 +1,9 @@
 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 
+	* mips.c (EF_MIPS_MACH): New E_MIPS_MACH_GS264E.
+
+2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
+
 	* mips.c (EF_MIPS_MACH): New E_MIPS_MACH_GS464E.
 
 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
diff --git a/elfcpp/mips.h b/elfcpp/mips.h
index 277300f..c724fd0 100644
--- a/elfcpp/mips.h
+++ b/elfcpp/mips.h
@@ -237,6 +237,7 @@ enum
   E_MIPS_MACH_LS2F = 0x00A10000,
   E_MIPS_MACH_GS464 = 0x00A20000,
   E_MIPS_MACH_GS464E = 0x00A30000,
+  E_MIPS_MACH_GS264E = 0x00A40000,
 };
 
 // MIPS architecture
diff --git a/gas/ChangeLog b/gas/ChangeLog
index a9413fa..8bb6ae8 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,11 @@
 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 
+	* config/tc-mips.c (ISA_HAS_ODD_SINGLE_FPR): Exclude CPU_GS264E.
+	(mips_cpu_info_table): Add gs264e descriptors.
+	* doc/as.texi (march table): Add gs264e.
+
+2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
+
 	* config/tc-mips.c (ISA_HAS_ODD_SINGLE_FPR): Exclude CPU_GS464E.
 	(mips_cpu_info_table): Add gs464e descriptors.
 	* doc/as.texi (march table): Add gs464e.
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index 9c0a1fd..c9fc6c6 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -423,7 +423,8 @@ static int mips_32bitmode = 0;
     || (ISA) == ISA_MIPS64R6		\
     || (CPU) == CPU_R5900)		\
    && ((CPU) != CPU_GS464		\
-    || (CPU) != CPU_GS464E))
+    || (CPU) != CPU_GS464E		\
+    || (CPU) != CPU_GS264E))
 
 /* Return true if ISA supports move to/from high part of a 64-bit
    floating-point register. */
@@ -19817,6 +19818,8 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
      ISA_MIPS64R2,	CPU_GS464 },
   { "gs464e",         0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT
      | ASE_LOONGSON_EXT2,	ISA_MIPS64R2,	CPU_GS464E },
+  { "gs264e",         0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT
+     | ASE_LOONGSON_EXT2 | ASE_MSA | ASE_MSA64,	ISA_MIPS64R2,	CPU_GS264E },
 
   /* Cavium Networks Octeon CPU core */
   { "octeon",	      0, 0,			ISA_MIPS64R2, CPU_OCTEON },
diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi
index 2682e36..7751ce0 100644
--- a/gas/doc/c-mips.texi
+++ b/gas/doc/c-mips.texi
@@ -439,6 +439,7 @@ loongson2e,
 loongson2f,
 gs464,
 gs464e,
+gs264e,
 octeon,
 octeon+,
 octeon2,
diff --git a/gold/mips.cc b/gold/mips.cc
index 12aa7de..0123fd7 100644
--- a/gold/mips.cc
+++ b/gold/mips.cc
@@ -3984,6 +3984,7 @@ class Target_mips : public Sized_target<size, big_endian>
     mach_mips_loongson_2f     = 3002,
     mach_mips_gs464           = 3003,
     mach_mips_gs464e          = 3004,
+    mach_mips_gs264e          = 3005,
     mach_mips_sb1             = 12310201, // octal 'SB', 01
     mach_mips_octeon          = 6501,
     mach_mips_octeonp         = 6601,
@@ -4149,6 +4150,7 @@ class Target_mips : public Sized_target<size, big_endian>
     this->add_extension(mach_mips_octeon2, mach_mips_octeonp);
     this->add_extension(mach_mips_octeonp, mach_mips_octeon);
     this->add_extension(mach_mips_octeon, mach_mipsisa64r2);
+    this->add_extension(mach_mips_gs264e, mach_mips_gs464e);
     this->add_extension(mach_mips_gs464e, mach_mips_gs464);
     this->add_extension(mach_mips_gs464, mach_mipsisa64r2);
 
@@ -8866,6 +8868,9 @@ Target_mips<size, big_endian>::elf_mips_mach(elfcpp::Elf_Word flags)
     case elfcpp::E_MIPS_MACH_GS464E:
       return mach_mips_gs464e;
 
+    case elfcpp::E_MIPS_MACH_GS264E:
+      return mach_mips_gs264e;
+
     case elfcpp::E_MIPS_MACH_OCTEON3:
       return mach_mips_octeon3;
 
@@ -12533,6 +12538,8 @@ Target_mips<size, big_endian>::elf_mips_mach_name(elfcpp::Elf_Word e_flags)
       return "mips:gs464";
     case elfcpp::E_MIPS_MACH_GS464E:
       return "mips:gs464e";
+    case elfcpp::E_MIPS_MACH_GS264E:
+      return "mips:gs264e";
     case elfcpp::E_MIPS_MACH_OCTEON:
       return "mips:octeon";
     case elfcpp::E_MIPS_MACH_OCTEON2:
diff --git a/include/ChangeLog b/include/ChangeLog
index 623c954..6c19b1d 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,5 +1,9 @@
 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 
+	* elf/mips.h (E_MIPS_MACH_XXX): New E_MIPS_MACH_GS264E.
+	* opcode/mips.h (CPU_XXX): New CPU_GS264E.
+
+2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 
 	* elf/mips.h (E_MIPS_MACH_XXX): New E_MIPS_MACH_GS464E.
 	* opcode/mips.h (CPU_XXX): New CPU_GS464E.
diff --git a/include/elf/mips.h b/include/elf/mips.h
index e27b6af..3858ee3 100644
--- a/include/elf/mips.h
+++ b/include/elf/mips.h
@@ -301,6 +301,7 @@ END_RELOC_NUMBERS (R_MIPS_maxext)
 #define E_MIPS_MACH_LS2F        0x00A10000
 #define E_MIPS_MACH_GS464       0x00A20000
 #define E_MIPS_MACH_GS464E	0x00A30000
+#define E_MIPS_MACH_GS264E	0x00A40000
 
 /* Processor specific section indices.  These sections do not actually
    exist.  Symbols with a st_shndx field corresponding to one of these
diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index 4ad65c9..fe8d16b 100644
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -1374,6 +1374,7 @@ static const unsigned int mips_isa_table[] = {
 #define CPU_LOONGSON_2F 3002
 #define CPU_GS464	3003
 #define CPU_GS464E	3004
+#define CPU_GS264E	3005
 #define CPU_OCTEON	6501
 #define CPU_OCTEONP	6601
 #define CPU_OCTEON2	6502
diff --git a/ld/ChangeLog b/ld/ChangeLog
index 9d1e02f..be69498 100644
--- a/ld/ChangeLog
+++ b/ld/ChangeLog
@@ -1,6 +1,11 @@
 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 
 	* testsuite/ld-mips-elf/mips-elf-flags.exp: Run good_combination
+	gs264e and gs464e.
+
+2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
+
+	* testsuite/ld-mips-elf/mips-elf-flags.exp: Run good_combination
 	gs464e and gs464.
 
 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
diff --git a/ld/testsuite/ld-mips-elf/mips-elf-flags.exp b/ld/testsuite/ld-mips-elf/mips-elf-flags.exp
index dcd33ba..385dca9 100644
--- a/ld/testsuite/ld-mips-elf/mips-elf-flags.exp
+++ b/ld/testsuite/ld-mips-elf/mips-elf-flags.exp
@@ -320,3 +320,7 @@ good_combination { "-march=gs464 -32" "-march=gs464e -32" }	\
 		 { gs464e o32 }					\
 		 MIPS64r2 "None"				\
 		 { "Loongson MMI ASE" "Loongson CAM ASE" "Loongson EXT ASE" "Loongson EXT2 ASE" }
+good_combination { "-march=gs264e -32" "-march=gs464e -32" }	\
+		 { gs264e o32 }					\
+		 MIPS64r2 "None"				\
+		 { "Loongson MMI ASE" "Loongson CAM ASE" "Loongson EXT ASE" "Loongson EXT2 ASE" }
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 6f338f8..f536bc4 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,9 @@
 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 
+	* mips-dis.c (mips_arch_choices): Add gs264e descriptors.
+
+2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
+
 	* mips-dis.c (mips_arch_choices): Add gs464e descriptors.
 
 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index 0f5799d..6991948 100644
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -645,6 +645,11 @@ const struct mips_arch_choice mips_arch_choices[] =
     | ASE_LOONGSON_EXT2, mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips3264,
     mips_hwr_names_numeric },
 
+  { "g264e",   1, bfd_mach_mips_gs464e, CPU_GS264E,
+    ISA_MIPS64R2, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT
+    | ASE_LOONGSON_EXT2 | ASE_MSA | ASE_MSA64, mips_cp0_names_numeric, NULL,
+    0, mips_cp1_names_mips3264, mips_hwr_names_numeric },
+
   { "octeon",   1, bfd_mach_mips_octeon, CPU_OCTEON,
     ISA_MIPS64R2 | INSN_OCTEON, 0, mips_cp0_names_numeric, NULL, 0,
     mips_cp1_names_mips3264, mips_hwr_names_numeric },